search for: constantpoolsdnod

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2008 Sep 13
2
[LLVMdev] Alignment of constant loads
...es alignment 0 > Alignment = getMVTAlignment(VT); > > Inside getMVTAlignment, the ABI alignment is retrieved for the given VT. > > It appears that constants are already aligned to the preferred > alignment, given this code in ScheduleDAG::AddOperand(): > > } else if (ConstantPoolSDNode *CP = > dyn_cast<ConstantPoolSDNode>(Op)) { > [...] > Align = TM.getTargetData()->getPreferredTypeAlignmentShift(Type); > > (note there is a curious FIXME there about alignment of vector types > -- I think this may be a relic since getPreferredTypeAlignmentShi...
2008 Sep 15
0
[LLVMdev] Alignment of constant loads
...alignment parameters to the getLoad/getExtLoad calls. > > If you move the handling of Alignment==0 out of ScheduleDAGEmit.cpp > and into SelectionDAG::getConstantPool, you can then have legalize > read the alignment from the node, instead of making its own > decision: > cast<ConstantPoolSDNode>(CPIdx)->getAlignment() > > I followed your suggestion but I've come across a bit of a snag. If you get the alignment in LegalizeDAG using: SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignme...
2008 Sep 18
2
[LLVMdev] store addrspace qualifier
Mon Ping, Thanks for the tip, but I can't for the life of me seem to get the Value from a StoreSDNode. From looking at the SelectionDAGNodes header file, the only class that has the getValue function call is SrcValueSDNode that returns a Value type. The only class that has getType is a ConstantPoolSDNode. I don't think that ConstantPoolSDNode is what I want and when I try to cast the getBasePtr().Val of the StoreSDNode to a SrcValueSDNode it asserts on: Assertion failed: isa<X>(Val) && "cast<Ty>() argument of incompatible type!" This is what I'm attemptin...
2008 Sep 12
0
[LLVMdev] Alignment of constant loads
...0) // Ensure that codegen never sees alignment 0 Alignment = getMVTAlignment(VT); Inside getMVTAlignment, the ABI alignment is retrieved for the given VT. It appears that constants are already aligned to the preferred alignment, given this code in ScheduleDAG::AddOperand(): } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) { [...] Align = TM.getTargetData()->getPreferredTypeAlignmentShift(Type); (note there is a curious FIXME there about alignment of vector types -- I think this may be a relic since getPreferredTypeAlignmentShift should not return ze...
2011 Jun 22
1
[LLVMdev] Mips backend -- Incorrect globaladdr/constpool address generation when bit 15 of address is set?
..., %hi($CPI1_0) // lwc1 $f0, %lo($CPI1_0)($2) if ((Addr.getOperand(0).getOpcode() == MipsISD::Hi || Addr.getOperand(0).getOpcode() == ISD::LOAD) && Addr.getOperand(1).getOpcode() == MipsISD::Lo) { SDValue LoVal = Addr.getOperand(1); if (dyn_cast<ConstantPoolSDNode>(LoVal.getOperand(0))) { Base = Addr.getOperand(0); Offset = LoVal.getOperand(0); return true; } } } This optimization folds the low 16 bits of the global address into the load offset, rather than generating a separate 'addiu' instruction. To...
2008 Sep 17
0
[LLVMdev] store addrspace qualifier
The address qualifier is stored in the type of %result. From that operand, you can get the Value and then call getType. The type for result should be a PointerType which you cast to a PointerType and get the getAddressSpace e.g. cast<PointerType>(Ty)->getAddressSpace() -- Mon Ping On Sep 17, 2008, at 1:06 PM, Villmow, Micah wrote: > How do I access the address qualifier
2008 Sep 17
2
[LLVMdev] store addrspace qualifier
How do I access the address qualifier from the store instruction. Given the following code: define void @test_unary_op_anegate(float %x, float addrspace(11)* %result) nounwind { entry: %neg = sub float -0.000000e+000, %x ; <float> [#uses=1] store float %neg, float addrspace(11)* %result ret void } When I attempt to generate this code, I'm
2011 Feb 20
0
[LLVMdev] ConstantPoolValue lifecycle question
I am investigating the leak in MC/ARM/elf-reloc-01.ll on the valgrind bot. It seems to be leaking two MachineConstantPoolValues. When a ConstantPoolSDNode is created with a ConstantPoolValue, it owns that ConstantPoolValue. In InstrEmitter::AddOperand(), the index of the CPV is taken from a MachineConstantPool, which has two cases: 1) This is a new constant, so a new entry is created. The MachineConstantPoolValue is freed in MachineConstantPool'...
2012 Dec 17
0
[LLVMdev] Query Regarding instruction ordering of passive nodes
...such that they are free to be placed anywhere while generating the instruction sequence. Is this related with above problem of debug location ? The list of passive nodes are :- ConstantSDNode ConstantFPSDNode RegisterSDNode RegisterMaskSDNode GlobalAddressSDNode BasicBlockSDNode FrameIndexSDNode ConstantPoolSDNode JumpTableSDNode ExternalSymbolSDNode BlockAddressSDNode MDNodeSDNode Thanks Karthik -------------- next part -------------- A non-text attachment was scrubbed... Name: gdb11531.s Type: application/octet-stream Size: 10377 bytes Desc: not available URL: <http://lists.llvm.org/pipermail/llvm-...
2006 Dec 19
3
[LLVMdev] alias-aware scheduling
...cast<ConstantSDNode>(Base.getOperand(1))) { + Base = Base.getOperand(0); + Offset += C->getValue(); + } + } + + // If it's any of the following then it can't alias with anything but itself. + return isa<FrameIndexSDNode>(Base) || + isa<ConstantPoolSDNode>(Base) || + isa<GlobalAddressSDNode>(Base); + } + + /* FIXME: copied from DAGCombiner.cpp */ + /// isAlias - Return true if there is any possibility that the two addresses + /// overlap. + bool isAlias(SDOperand Ptr1, int64_t Size1, + const Value *SrcValue1, i...
2009 May 21
0
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote: > Can you explain why you chose the approach of using a new pass? > I pictured removing LegalizeDAG's type legalization code would > mostly consist of finding all the places that use TLI.getTypeAction > and just deleting code for handling its Expand and Promote. Are you > anticipating something more
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On May 20, 2009, at 1:34 PM, Eli Friedman wrote: > On Wed, May 20, 2009 at 1:19 PM, Eli Friedman > <eli.friedman at gmail.com> wrote: > >> Per subject, this patch adding an additional pass to handle vector >> >> operations; the idea is that this allows removing the code from >> >> LegalizeDAG that handles illegal types, which should be a significant
2009 May 21
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
...SignSet, Four, Zero); - uint64_t FF = 0x5f800000ULL; - if (TLI.isLittleEndian()) FF <<= 32; - Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); - - SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); - unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); - CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset); - Alignment = std::min(Alignment, 4u); - SDValue FudgeInReg; - if (DestTy == MVT::f32) - FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx, -...