search for: common_cfg

...) > + goto next; > + > + IFC_DBG(&dev->dev, "read PCI config: config type: %u, PCI bar: %u,\ > + PCI bar offset: %u, PCI config len: %u.\n", > + cap.cfg_type, cap.bar, cap.offset, cap.length); > + > + switch (cap.cfg_type) { > + case VIRTIO_PCI_CAP_COMMON_CFG: > + hw->common_cfg = get_cap_addr(hw, &cap); > + IFC_INFO(&dev->dev, "hw->common_cfg = %p.\n", > + hw->common_cfg); > + break; > + case VIRTIO_PCI_CAP_NOTIFY_CFG: > + pci_read_config_dword(dev, pos + sizeof(cap), > + &hw...

...) > + goto next; > + > + IFC_DBG(&dev->dev, "read PCI config: config type: %u, PCI bar: %u,\ > + PCI bar offset: %u, PCI config len: %u.\n", > + cap.cfg_type, cap.bar, cap.offset, cap.length); > + > + switch (cap.cfg_type) { > + case VIRTIO_PCI_CAP_COMMON_CFG: > + hw->common_cfg = get_cap_addr(hw, &cap); > + IFC_INFO(&dev->dev, "hw->common_cfg = %p.\n", > + hw->common_cfg); > + break; > + case VIRTIO_PCI_CAP_NOTIFY_CFG: > + pci_read_config_dword(dev, pos + sizeof(cap), > + &hw...

...) > + goto next; > + > + IFC_DBG(&dev->dev, "read PCI config: config type: %u, PCI bar: %u,\ > + PCI bar offset: %u, PCI config len: %u.\n", > + cap.cfg_type, cap.bar, cap.offset, cap.length); > + > + switch (cap.cfg_type) { > + case VIRTIO_PCI_CAP_COMMON_CFG: > + hw->common_cfg = get_cap_addr(hw, &cap); > + IFC_INFO(&dev->dev, "hw->common_cfg = %p.\n", > + hw->common_cfg); > + break; > + case VIRTIO_PCI_CAP_NOTIFY_CFG: > + pci_read_config_dword(dev, pos + sizeof(cap), > + &hw...

...tructure offset within the bar */ s/the bar/the BAR/ (to match comment below). > +static void viommu_pci_parse_topology(struct pci_dev *dev) > +{ > + int ret; > + u32 features; > + void __iomem *regs, *common_regs; > + struct viommu_cap_config cap = {0}; > + struct virtio_pci_common_cfg __iomem *common_cfg; > + > + /* > + * The virtio infrastructure might not be loaded at this point. We need > + * to access the BARs ourselves. > + */ > + ret = viommu_pci_find_capability(dev, VIRTIO_PCI_CAP_COMMON_CFG, &cap); > + if (!ret) { > + pci_warn(dev, "c...

...tructure offset within the bar */ s/the bar/the BAR/ (to match comment below). > +static void viommu_pci_parse_topology(struct pci_dev *dev) > +{ > + int ret; > + u32 features; > + void __iomem *regs, *common_regs; > + struct viommu_cap_config cap = {0}; > + struct virtio_pci_common_cfg __iomem *common_cfg; > + > + /* > + * The virtio infrastructure might not be loaded at this point. We need > + * to access the BARs ourselves. > + */ > + ret = viommu_pci_find_capability(dev, VIRTIO_PCI_CAP_COMMON_CFG, &cap); > + if (!ret) { > + pci_warn(dev, "c...

...) > + goto next; > + > + IFC_DBG(&dev->dev, "read PCI config: config type: %u, PCI bar: %u,\ > + PCI bar offset: %u, PCI config len: %u.\n", > + cap.cfg_type, cap.bar, cap.offset, cap.length); > + > + switch (cap.cfg_type) { > + case VIRTIO_PCI_CAP_COMMON_CFG: > + hw->common_cfg = get_cap_addr(hw, &cap); > + IFC_INFO(&dev->dev, "hw->common_cfg = %p.\n", > + hw->common_cfg); > + break; > + case VIRTIO_PCI_CAP_NOTIFY_CFG: > + pci_read_config_dword(dev, pos + sizeof(cap), > + &hw...

..."config type: %u.\n" > + "PCI bar: %u.\n" > + "PCI bar offset: %u.\n" > + "PCI config len: %u.\n", > + cap.cfg_type, cap.bar, > + cap.offset, cap.length); > + > + switch (cap.cfg_type) { > + case VIRTIO_PCI_CAP_COMMON_CFG: > + hw->common_cfg = get_cap_addr(hw, &cap); > + IFC_INFO(&dev->dev, "hw->common_cfg = %p.\n", > + hw->common_cfg); > + break; > + case VIRTIO_PCI_CAP_NOTIFY_CFG: > + pci_read_config_dword(dev, pos + sizeof(cap), > + &hw->no...

...%u.\n" >>> +??????????????????? "PCI config len: %u.\n", >>> +??????????????????? cap.cfg_type, cap.bar, >>> +??????????????????? cap.offset, cap.length); >>> + >>> +??????? switch (cap.cfg_type) { >>> +??????? case VIRTIO_PCI_CAP_COMMON_CFG: >>> +??????????? hw->common_cfg = get_cap_addr(hw, &cap); >>> +??????????? IFC_INFO(&dev->dev, "hw->common_cfg = %p.\n", >>> +??????????????????? hw->common_cfg); >>> +??????????? break; >>> +??????? case VIRTIO_PCI_CAP_NOT...

...rs/vdpa/ifcvf/ifcvf_base.c +++ b/drivers/vdpa/ifcvf/ifcvf_base.c @@ -329,31 +329,49 @@ int ifcvf_set_vq_state(struct ifcvf_hw *hw, u16 qid, u16 num) return 0; } -static int ifcvf_hw_enable(struct ifcvf_hw *hw) +void ifcvf_set_vq_num(struct ifcvf_hw *hw, u16 qid, u32 num) { - struct virtio_pci_common_cfg __iomem *cfg; - u32 i; + struct virtio_pci_common_cfg __iomem *cfg = hw->common_cfg; - cfg = hw->common_cfg; - for (i = 0; i < hw->nr_vring; i++) { - if (!hw->vring[i].ready) - break; + vp_iowrite16(qid, &cfg->queue_select); + vp_iowrite16(num, &cfg->queue_size); +...

...continue; + + cap->bar = bar; + pci_read_config_dword(dev, pos + VPCI_FIELD(length), + &cap->length); + pci_read_config_dword(dev, pos + VPCI_FIELD(offset), + &cap->offset); + + return pos; + } + return 0; +} + +static int viommu_pci_reset(struct virtio_pci_common_cfg __iomem *cfg) +{ + u8 status; + ktime_t timeout = ktime_add_ms(ktime_get(), 100); + + iowrite8(0, &cfg->device_status); + while ((status = ioread8(&cfg->device_status)) != 0 && + ktime_before(ktime_get(), timeout)) + msleep(1); + + return status ? -ETIMEDOUT : 0; +} +...

...onfig_dword(dev, pos + VPCI_FIELD(length), > + &cap->length); > + pci_read_config_dword(dev, pos + VPCI_FIELD(offset), > + &cap->offset); > + > + return pos; > + } > + return 0; > +} > + > +static int viommu_pci_reset(struct virtio_pci_common_cfg __iomem *cfg) > +{ > + u8 status; > + ktime_t timeout = ktime_add_ms(ktime_get(), 100); > + > + iowrite8(0, &cfg->device_status); > + while ((status = ioread8(&cfg->device_status)) != 0 && > + ktime_before(ktime_get(), timeout)) > + msleep(1); &...

...rs/vdpa/ifcvf/ifcvf_base.c +++ b/drivers/vdpa/ifcvf/ifcvf_base.c @@ -329,31 +329,49 @@ int ifcvf_set_vq_state(struct ifcvf_hw *hw, u16 qid, u16 num) return 0; } -static int ifcvf_hw_enable(struct ifcvf_hw *hw) +void ifcvf_set_vq_num(struct ifcvf_hw *hw, u16 qid, u32 num) { - struct virtio_pci_common_cfg __iomem *cfg; - u32 i; + struct virtio_pci_common_cfg __iomem *cfg = hw->common_cfg; - cfg = hw->common_cfg; - for (i = 0; i < hw->nr_vring; i++) { - if (!hw->vring[i].ready) - break; + vp_iowrite16(qid, &cfg->queue_select); + vp_iowrite16(num, &cfg->queue_size); +...

Add a topology description to the virtio-iommu driver and enable x86 platforms. Since [v2] we have made some progress on adding ACPI support for virtio-iommu, which is the preferred boot method on x86. It will be a new vendor-agnostic table describing para-virtual topologies in a minimal format. However some platforms don't use either ACPI or DT for booting (for example microvm), and will

Add a topology description to the virtio-iommu driver and enable x86 platforms. Since [v2] we have made some progress on adding ACPI support for virtio-iommu, which is the preferred boot method on x86. It will be a new vendor-agnostic table describing para-virtual topologies in a minimal format. However some platforms don't use either ACPI or DT for booting (for example microvm), and will

...bar/the BAR/ (to match comment below). > > > +static void viommu_pci_parse_topology(struct pci_dev *dev) > > +{ > > + int ret; > > + u32 features; > > + void __iomem *regs, *common_regs; > > + struct viommu_cap_config cap = {0}; > > + struct virtio_pci_common_cfg __iomem *common_cfg; > > + > > + /* > > + * The virtio infrastructure might not be loaded at this point. We need > > + * to access the BARs ourselves. > > + */ > > + ret = viommu_pci_find_capability(dev, VIRTIO_PCI_CAP_COMMON_CFG, &cap); > > + if (!r...

Formerly, ifcvf driver has implemented a lazy-initialization mechanism for the virtqueues and other config space contents, it would store all configurations that passed down from the userspace, then load them to the device config space upon DRIVER_OK. This can not serve live migration, so this series implement an immediate initialization mechanism, which means rather than the former store-load

Formerly, ifcvf driver has implemented a lazy-initialization mechanism for the virtqueues and other config space contents, it would store all configurations that passed down from the userspace, then load them to the device config space upon DRIVER_OK. This can not serve live migration, so this series implement an immediate initialization mechanism, which means rather than the former store-load

...res(struct ifcvf_hw *hw) return features; } -u64 ifcvf_get_features(struct ifcvf_hw *hw) +/* return provisioned vDPA dev features */ +u64 ifcvf_get_dev_features(struct ifcvf_hw *hw) { return hw->dev_features; } +u64 ifcvf_get_driver_features(struct ifcvf_hw *hw) +{ + struct virtio_pci_common_cfg __iomem *cfg = hw->common_cfg; + u32 features_lo, features_hi; + u64 features; + + vp_iowrite32(0, &cfg->device_feature_select); + features_lo = vp_ioread32(&cfg->guest_feature); + + vp_iowrite32(1, &cfg->device_feature_select); + features_hi = vp_ioread32(&cfg->guest...

..._dev_config(struct ifcvf_hw *hw, u64 offset, >>>> + void *dst, int length) >>>> +{ >>>> + int i; >>>> + u8 *p; >>>> + u8 old_gen, new_gen; >>>> + >>>> + do { >>>> + old_gen = ioread8(&hw->common_cfg->config_generation); >>>> + >>>> + p = dst; >>>> + for (i = 0; i < length; i++) >>>> + *p++ = ioread8((u8 *)hw->dev_cfg + offset + i); >>>> + >>>> + new_gen = ioread8(&hw->common_cfg->config_generation);...

...;> + void *dst, int length) >>>>>> +{ >>>>>> + int i; >>>>>> + u8 *p; >>>>>> + u8 old_gen, new_gen; >>>>>> + >>>>>> + do { >>>>>> + old_gen = ioread8(&hw->common_cfg->config_generation); >>>>>> + >>>>>> + p = dst; >>>>>> + for (i = 0; i < length; i++) >>>>>> + *p++ = ioread8((u8 *)hw->dev_cfg + offset + i); >>>>>> + >>>>>> + new_gen = ioread...