search for: codeaurora

Displaying 20 results from an estimated 2026 matches for "codeaurora".

2017 Jul 20
2
error:Ran out of lanemask bits to represent subregisterr
...e R_CASS definition is as follows: class R_CASS<string n, bits<16> Enc, list<Register> subregs = []> : Register<n> { let Namespace = "X86"; let HWEncoding = Enc; let SubRegs = subregs; } On Thu, Jul 20, 2017 at 4:14 AM, Krzysztof Parzyszek < kparzysz at codeaurora.org> wrote: > I tried reproducing the problem, but the file doesn't have everything I > need (the class R_CLASS is not defined for example). > > Craig's getLane patch fixes the shifts, but if you want to use a larger > type than uint64_t, there is more work to do. I'l...
2016 Mar 24
1
[PATCH] D15965: Add support for dumping relocations in non-relocatable files
...dress so I’ll have to also find its containing section and add this in just so llvm-objdump can later subtract it. Can you detail why this is a better plan? From: Rafael Espíndola [mailto:rafael.espindola at gmail.com] Sent: Thursday, March 24, 2016 3:13 PM To: Colin LeMahieu <colinl at codeaurora.org> Cc: llvm-commits <llvm-commits at lists.llvm.org>; Shankar Easwaran <shankare at codeaurora.org>; Hemant Kulkarni <khemant at codeaurora.org>; reviews+D15965+public+319b19c852e3c4e3 at reviews.llvm.org Subject: RE: [PATCH] D15965: Add support for dumping relocations in non...
2017 Nov 10
5
[RFC] Enable Partial Inliner by default
.... The problem is that the crashes happen whilst LTO is used. One thing I am sure about IR is broken at compile time. Thanks, Evgeny From: Graham Yiu <gyiu at ca.ibm.com> Date: Friday, 10 November 2017 at 16:09 To: Evgeny Astigeevich <Evgeny.Astigeevich at arm.com> Cc: "junbuml at codeaurora.org" <junbuml at codeaurora.org>, "llvm-dev at lists.llvm.org" <llvm-dev at lists.llvm.org>, nd <nd at arm.com>, Tobias Grosser <tobias.grosser at inf.ethz.ch> Subject: Re: [llvm-dev] [RFC] Enable Partial Inliner by default Hi Evgeny, I just realized that i...
2017 Jul 19
5
error:Ran out of lanemask bits to represent subregisterr
...mp; RegNo <= X86::XMM31) || fatal error: too many errors emitted, stopping now [-ferror-limit=] 20 errors generated. When i comment out the line to construct 65536 bit register in registerinfo.td. it run fine. What to do? On Thu, Jul 20, 2017 at 2:36 AM, Krzysztof Parzyszek < kparzysz at codeaurora.org> wrote: > Those couldn't be done generically, that's why the asserts were added. > > -Krzysztof > > On 7/19/2017 4:30 PM, Craig Topper wrote: > >> What about the static asserts protecting a Log call and another in the >> parser? >> >&gt...
2017 Nov 10
0
[RFC] Enable Partial Inliner by default
...I can use to reproduce? Cheers, Graham Yiu LLVM Compiler Development IBM Toronto Software Lab Office: (905) 413-4077 C2-707/8200/Markham Email: gyiu at ca.ibm.com From: Graham Yiu/Toronto/IBM To: Evgeny Astigeevich <Evgeny.Astigeevich at arm.com> Cc: "junbuml at codeaurora.org" <junbuml at codeaurora.org>, "llvm-dev at lists.llvm.org" <llvm-dev at lists.llvm.org>, nd <nd at arm.com>, "Tobias Grosser" <tobias.grosser at inf.ethz.ch> Date: 11/08/2017 06:00 PM Subject: Re: [llvm-dev] [RFC]...
2016 Apr 21
2
[LICM][MemorySSA] Converting LICM pass to use MemorySSA to avoid AliasSet collapse issue
...-- Geoff Berry Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project From: George Burgess [mailto:gbiv at google.com] Sent: Wednesday, April 20, 2016 3:29 PM To: Geoff Berry <gberry at codeaurora.org> Cc: Daniel Berlin <dberlin at dberlin.org>; llvm-dev <llvm-dev at lists.llvm.org> Subject: Re: [LICM][MemorySSA] Converting LICM pass to use MemorySSA to avoid AliasSet collapse issue Hi! > readonly calls are treated as clobbers by MemorySSA which leads to extra walki...
2018 Aug 24
3
[assembler + debuginfo] interaction with .file directive and debuginfo
...ready exists, then reporting that as a > bug is appropriate. I can't say I'd be able to find time to try to *fix* > it before October, as I'm already over-committed, but I'd anticipate > getting to it around that time. > > --paulr > > > > *From:* bcain at codeaurora.org [mailto:bcain at codeaurora.org] > *Sent:* Thursday, August 23, 2018 3:18 PM > *To:* llvm-dev at lists.llvm.org > *Cc:* Robinson, Paul > *Subject:* [assembler + debuginfo] interaction with .file directive and > debuginfo > > > > [ I discussed this briefly with Paul of...
2017 Nov 02
13
[RFC] Enable Partial Inliner by default
...s were done with '-O3 -m64 -fexperimental-new-pass-manager'. Graham Yiu LLVM Compiler Development IBM Toronto Software Lab Office: (905) 413-4077 C2-707/8200/Markham Email: gyiu at ca.ibm.com From: Graham Yiu/Toronto/IBM To: llvm-dev at lists.llvm.org Cc: junbuml at codeaurora.org, xinliangli at gmail.com Date: 11/02/2017 05:26 PM Subject: [RFC] Enable Partial Inliner by default Hello, I'd like to propose turning on the partial inliner (-enable-partial-inlining) by default. We've seen small gains on SPEC2006/2017 runtimes as well as lnt compile-ti...
2016 Apr 28
2
Assertion in MachineScheduler.cpp
On 4/28/2016 2:11 PM, Rail Shafigulin wrote: > > On Thu, Apr 28, 2016 at 6:13 AM, Krzysztof Parzyszek > <kparzysz at codeaurora.org <mailto:kparzysz at codeaurora.org>> wrote: > > > IIRC, > > What is IIRC? If I remember correctly... -Krzysztof -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
2017 Jul 19
2
error:Ran out of lanemask bits to represent subregisterr
...s if i need to replace each occurrence of unsigned with uint64_t. Should i do it for complete llvm folder or codegen only?? i am continuously getting such errors which require changing unsigned with uint64_t. What to do now??? On Thu, Jul 20, 2017 at 1:03 AM, Krzysztof Parzyszek < kparzysz at codeaurora.org> wrote: > It is possible that you have more than 64 lanes. In such case you would > need to reimplement LaneBitmask with a larger underlying type. Most of the > functionality is already localized to the header file, the only exception > may be the "getAsInteger" functi...
2016 Apr 20
4
[LICM][MemorySSA] Converting LICM pass to use MemorySSA to avoid AliasSet collapse issue
...-- Geoff Berry Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project From: Daniel Berlin [mailto:dberlin at dberlin.org] Sent: Wednesday, April 20, 2016 1:06 PM To: Geoff Berry <gberry at codeaurora.org>; George Burgess <gbiv at google.com> Cc: llvm-dev <llvm-dev at lists.llvm.org> Subject: Re: [LICM][MemorySSA] Converting LICM pass to use MemorySSA to avoid AliasSet collapse issue On Wed, Apr 20, 2016 at 9:58 AM, Geoff Berry <gberry at codeaurora.org <mailto:gbe...
2017 Nov 13
2
[RFC] Enable Partial Inliner by default
...-dev <llvm-dev-bounces at lists.llvm.org> on behalf of Evgeny Astigeevich via llvm-dev <llvm-dev at lists.llvm.org> Reply-To: Evgeny Astigeevich <Evgeny.Astigeevich at arm.com> Date: Saturday, 11 November 2017 at 17:21 To: Graham Yiu <gyiu at ca.ibm.com> Cc: "junbuml at codeaurora.org" <junbuml at codeaurora.org>, "llvm-dev at lists.llvm.org" <llvm-dev at lists.llvm.org>, Tobias Grosser <tobias.grosser at inf.ethz.ch>, nd <nd at arm.com> Subject: Re: [llvm-dev] [RFC] Enable Partial Inliner by default Hi Graham, I’ve got results of ben...
2017 Aug 14
2
[ScalarEvolution][SCEV] no-wrap flags dependent on order of getSCEV() calls
> On Aug 14, 2017, at 7:35 AM, Geoff Berry <gberry at codeaurora.org> wrote: > > Hi Sanjoy, > > [adding Adam since I believe he added the original FIXME to preserve SCEV > in LoopDataPrefetch] For record, that wasn’t me. It was there from the beginning when Hal added the PPC-specific pass. Adam > > On 8/14/2017 1:36 AM, San...
2015 May 20
3
[LLVMdev] Empty emails from phabricator
Phabricator seems to like to send emails with zero content to the list with relatively high frequency, like this: > From: Ikhlas Ajbar <iajbar at codeaurora.org> > Subject: Re: [PATCH] Remove unused function HasPICArg(). > To: iajbar at codeaurora.org, bcahoon at codeaurora.org > Cc: llvm-commits at cs.uiuc.edu > Date: Tue, 19 May 2015 18:29:30 +0000 (6 hours, 21 minutes, 32 seconds ago) > Reply-To: reviews+D9775+public+5835e7bc078b3e...
2014 Dec 27
2
[LLVMdev] How to use BlockFrequency in inter-procedural context?
...ogically over the call graph, how representative will be the info if one just wants to use in a comparative sense ? -Dibyendu Sent from my Windows Phone ________________________________ From: Xinliang David Li<mailto:xinliangli at gmail.com> Sent: ‎12/‎27/‎2014 10:05 AM To: ibaev at codeaurora.org<mailto:ibaev at codeaurora.org> Cc: llvmdev<mailto:llvmdev at cs.uiuc.edu> Subject: Re: [LLVMdev] How to use BlockFrequency in inter-procedural context? On Fri, Dec 26, 2014 at 7:12 PM, <ibaev at codeaurora.org<mailto:ibaev at codeaurora.org>> wrote: The BlockFrequency...
2018 Apr 04
2
[RFC] Adding function attributes to represent codegen optimization level
Sorry, my reply “to all” left out LLVM-Dev From: Martin J. O'Riordan [mailto:MartinO at theheart.ie] Sent: 04 April 2018 16:41 To: 'David Blaikie' <dblaikie at gmail.com>; 'mcrosier at codeaurora.org' <mcrosier at codeaurora.org>; 'Chandler Carruth' <chandlerc at gmail.com>; 'Eric Christopher' <echristo at gmail.com> Subject: RE: [llvm-dev] [RFC] Adding function attributes to represent codegen optimization level Would implementing GCC’s ‘__attribute...
2015 Feb 04
2
[LLVMdev] Question on Machine Combiner Pass
Ping From: Mandeep Singh Grang [mailto:mgrang at codeaurora.org] Sent: Tuesday, February 03, 2015 4:34 PM To: 'llvmdev at cs.uiuc.edu' Cc: 'ghoflehner at apple.com'; 'apazos at codeaurora.org'; mgrang at codeaurora.org Subject: Question on Machine Combiner Pass Hi, In the file lib/CodeGen/MachineCombiner.cpp I see th...
2015 Nov 20
2
[AArch64] bug in shrink-wrapping
...ud.degrandmaison at arm.com> wrote: > > +CC llvm-dev > >> -----Original Message----- >> From: Arnaud A. de Grandmaison [mailto:arnaud.degrandmaison at arm.com] >> Sent: 20 November 2015 15:28 >> To: 'qcolombet at apple.com' >> Cc: 'haicheng at codeaurora.org' >> Subject: RE: [llvm-dev] [AArch64] bug in shrink-wrapping >> >> Now with memory leak addressed. >> >> Cheers, >> Arnaud >> >>> -----Original Message----- >>> From: Arnaud A. de Grandmaison >> [mailto:arnaud.degrandmaiso...
2017 Jul 19
2
error:Ran out of lanemask bits to represent subregisterr
LaneMask isn't as self contained as it should be. 64 bits is enough here. The problem is accidental leaking of the current size. For example there was a hard coded compare with 32 in tablegen until I fixed it recently. On Wed, Jul 19, 2017 at 1:36 PM Krzysztof Parzyszek <kparzysz at codeaurora.org> wrote: > LaneBitmask should be self-contained. If 64 bits aren't enough, there > is no point in using uint64_t, you need something wider. > > -Krzysztof > > On 7/19/2017 3:25 PM, hameeza ahmed wrote: > > You are right. Regarding lanes i can comment only...
2017 Jun 27
4
My experience using -DLLVM_BUILD_INSTRUMENTED_COVERAGE to generate coverage
...80/coverage/coverage-reports/llvm/coverage/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R at 2/llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp.html#L512> > On Jun 27, 2017, at 2:40 PM, Friedman, Eli <efriedma at codeaurora.org> wrote: > > I get a bunch of unreadable binary. Output piped to "less": > > String dump of section '__llvm_prf_names': > [ 2] #<CA>^Ex<DA><D4>is<E3>(^Z<EF>^O<DD>^P<A9><D5><F7><9B><CB>...