search for: cmpwi

...# InlineAsm Start --> isync # InlineAsm End lwz 3, 44(1) lwz 3, 44(1) cmpwi 0, 3, -1 cmpwi 0, 3, -1 I would like to insert Code (like the isync) in the asm output of the llc. What is the best way, or easiest to do this. llc -filetype=asm -march=ppc32 -o=test.s test.bc With best regards, - Michael -------------- next part...

...ird code on the LLVM 1.6 PowerPC backend: LBB_matches_1: ; regex6 lbz r4, 0(r3) LBB_matches_2: ; NodeBlock rlwinm r5, r4, 0, 24, 31 cmplwi cr0, r5, 98 blt cr0, LBB_matches_4 ; LeafBlock LBB_matches_3: ; LeafBlock1 rlwinm r4, r4, 0, 24, 31 cmpwi cr0, r4, 98 beq cr0, LBB_matches_8 ; ret_true b LBB_matches_5 ; NewDefault LBB_matches_4: ; LeafBlock rlwinm r4, r4, 0, 24, 31 cmpwi cr0, r4, 97 beq cr0, LBB_matches_8 ; ret_true LBB_matches_5: ; NewDefault LBB_matches_6: ; loop_step I'm partic...

...           # InlineAsm > Start > >                                                -->          isync > >                                                                # InlineAsm > End > >         lwz 3, 44(1)                                lwz 3, 44(1) > >         cmpwi 0, 3, -1                           cmpwi 0, 3, -1 > > > > I would like to insert Code (like the isync) in the asm output of the llc. > What is the best way, or easiest to do this. > Well, inlined assembly, of course. :-) Make sure to mark it as "volatile". -bw

...rough LBB1_4, and now it is falling on LBB1_9. LBB1_3: ;no_exit lis r4, 21845 ori r4, r4, 21846 mulhw r4, r2, r4 addi r5, r2, -1 li r6, -1 srwi r6, r4, 31 add r4, r4, r6 mulli r4, r4, 3 li r6, 1 subf r2, r4, r2 cmpwi cr0, r2, 0 beq cr0, LBB1_9 ;no_exit LBB1_7: ;no_exit mr r2, r6 LBB1_8: ;no_exit cmpwi cr0, r5, 0 add r2, r2, r3 bgt cr0, LBB1_5 ;no_exit.no_exit_llvm_crit_edge LBB1_9: ;no_exit mr r2, r6 b LBB1_8 ;no_exit LBB1_4: ;no_exit.loopexit_llvm_...

...           # InlineAsm > Start > >                                                -->          isync > >                                                                # InlineAsm > End > >         lwz 3, 44(1)                                lwz 3, 44(1) > >         cmpwi 0, 3, -1                           cmpwi 0, 3, -1 > > > > I would like to insert Code (like the isync) in the asm output of the llc. > What is the best way, or easiest to do this. > Well, inlined assembly, of course. :-) Make sure to mark it as "volatile". -bw ________...

...> > LBB_matches_1: ; regex6 > lbz r4, 0(r3) > LBB_matches_2: ; NodeBlock > rlwinm r5, r4, 0, 24, 31 > cmplwi cr0, r5, 98 > blt cr0, LBB_matches_4 ; LeafBlock > LBB_matches_3: ; LeafBlock1 > rlwinm r4, r4, 0, 24, 31 > cmpwi cr0, r4, 98 > beq cr0, LBB_matches_8 ; ret_true > b LBB_matches_5 ; NewDefault > LBB_matches_4: ; LeafBlock > rlwinm r4, r4, 0, 24, 31 > cmpwi cr0, r4, 97 > beq cr0, LBB_matches_8 ; ret_true > LBB_matches_5: ; NewDefault > LBB_matc...

...gt; LBB1_3: ;no_exit > lis r4, 21845 > ori r4, r4, 21846 > mulhw r4, r2, r4 > addi r5, r2, -1 > li r6, -1 > srwi r6, r4, 31 > add r4, r4, r6 > mulli r4, r4, 3 > li r6, 1 > subf r2, r4, r2 > cmpwi cr0, r2, 0 > beq cr0, LBB1_9 ;no_exit > LBB1_7: ;no_exit > mr r2, r6 > LBB1_8: ;no_exit > cmpwi cr0, r5, 0 > add r2, r2, r3 > bgt cr0, LBB1_5 ;no_exit.no_exit_llvm_crit_edge > LBB1_9: ;no_exit > mr r2, r6 > b LBB1_8...

...the old value in the lock, so we succeeded + * in getting the lock if the return value is 0. + */ +static inline unsigned long __arch_spin_trylock(arch_spinlock_t *lock) +{ + unsigned long tmp, token; + + token = LOCK_TOKEN; + __asm__ __volatile__( +"1: " PPC_LWARX(%0,0,%2,1) "\n\ + cmpwi 0,%0,0\n\ + bne- 2f\n\ + stwcx. %1,0,%2\n\ + bne- 1b\n" + PPC_ACQUIRE_BARRIER +"2:" + : "=&r" (tmp) + : "r" (token), "r" (&lock->slock) + : "cr0", "memory"); + + return tmp; +} + +static inline int arch_spin_trylock(arc...

On Thu, 16 Mar 2006, Eric Kidd wrote: > Hello! I'm compiling code which uses pointers as iterators. For some > reason--probably a silly misunderstanding of the docs--I can't eliminate > duplicate pointer loads. I'll probably figure this out eventually, but if > somebody else sees the answer instantly, I certainly won't complain. :-) There are no stupid questions.

> If you don't want critical edges in the machine code CFG, you're going to > have to write a machine code CFG critical edge splitting pass: LLVM > doesn't currently have one. > > -Chris Hey guys, I've coded a pass to break the critical edges of the machine control flow graph. The program works fine, but I am sure it is not the right way of implementing it.

Hello! I'm compiling code which uses pointers as iterators. For some reason--probably a silly misunderstanding of the docs--I can't eliminate duplicate pointer loads. I'll probably figure this out eventually, but if somebody else sees the answer instantly, I certainly won't complain. :-) Here are the optimizers I'm running: opt -f -simplifycfg -dce -instcombine

On Tue, 4 Jul 2006, Fernando Magno Quintao Pereira wrote: > However, it does not remove all the critical edges. I am getting a very > weird dataflow graph (even without the Break Critical edges pass). The > dataflow generated by MachineFunction::dump() for the program below is > given here: > http://compilers.cs.ucla.edu/fernando/projects/soc/images/loop_no_crit2.pdf ... > The

v2 is updated to account for feedback from Will, Peter, and Waiman (thank you), and trims off a couple of RFC and unrelated patches. Thanks, Nick Nicholas Piggin (6): powerpc/powernv: must include hvcall.h to get PAPR defines powerpc/pseries: move some PAPR paravirt functions to their own file powerpc: move spinlock implementation to simple_spinlock powerpc/64s: implement queued

Updated with everybody's feedback (thanks all), and more performance results. What I've found is I might have been measuring the worst load point for the paravirt case, and by looking at a range of loads it's clear that queued spinlocks are overall better even on PV, doubly so when you look at the generally much improved worst case latencies. I have defaulted it to N even though

On 2008-06-11, at 13:16, Gary Benson wrote: > Duncan Sands wrote: > >> Can you please attach IR which can be compiled to an executable >> (and shows the problem). > > I've been generating functions using a builder and then compiling > them with ExecutionEngine::getPointerToFunction(). Is there some way > I can get compilable IR from that?

Duncan Sands wrote: > Can you please attach IR which can be compiled > to an executable (and shows the problem). I've been generating functions using a builder and then compiling them with ExecutionEngine::getPointerToFunction(). Is there some way I can get compilable IR from that? Cheers, Gary -- http://gbenson.net/

This series adds an option to use queued spinlocks for powerpc, and makes it the default for the Book3S-64 subarch. This effort starts with the generic code so it's very simple but still very performant. There are optimisations that can be made to slowpaths, but I think it's better to attack those incrementally if/when we find things, and try to add the improvements to generic code as

v3 is updated to use __pv_queued_spin_unlock, noticed by Waiman (thank you). Thanks, Nick Nicholas Piggin (6): powerpc/powernv: must include hvcall.h to get PAPR defines powerpc/pseries: move some PAPR paravirt functions to their own file powerpc: move spinlock implementation to simple_spinlock powerpc/64s: implement queued spinlocks and rwlocks powerpc/pseries: implement paravirt

v3 is updated to use __pv_queued_spin_unlock, noticed by Waiman (thank you). Thanks, Nick Nicholas Piggin (6): powerpc/powernv: must include hvcall.h to get PAPR defines powerpc/pseries: move some PAPR paravirt functions to their own file powerpc: move spinlock implementation to simple_spinlock powerpc/64s: implement queued spinlocks and rwlocks powerpc/pseries: implement paravirt

On Tue, 4 May 2004, Patrick Flanagan wrote: > I was able to run through all the C/C++ benchmarks in SPEC using LLVM. > I'm on OS X 10.3.3. I did a quick comparison between LLVM (latest from > CVS as of 4/27) and gcc 3.3 (Apple's build 20030304). For simplicity's > sake, the only flag I used was -O3 for each compiler and I was using > the C backend to generate native