Displaying 3 results from an estimated 3 matches for "cmpswap".
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cmp_swap
2016 Mar 28
0
RFC: atomic operations on SI+
...> index 593300f..d99b013 100644
> --- a/lib/Target/AMDGPU/CIInstructions.td
> +++ b/lib/Target/AMDGPU/CIInstructions.td
> @@ -156,7 +156,7 @@ defm FLAT_ATOMIC_SWAP : FLAT_ATOMIC <
> flat<0x30, 0x40>, "flat_atomic_swap", VGPR_32
> >;
> defm FLAT_ATOMIC_CMPSWAP : FLAT_ATOMIC <
> - flat<0x31, 0x41>, "flat_atomic_cmpswap", VGPR_32, VReg_64
> + flat<0x31, 0x41>, "flat_atomic_cmpswap", VReg_64
> >;
> defm FLAT_ATOMIC_ADD : FLAT_ATOMIC <
> flat<0x32, 0x42>, "flat_atomic_add", VGPR_3...
2016 Mar 25
2
RFC: atomic operations on SI+
Hi Tom, Matt,
I'm working on a project that needs few coherent atomic operations (HSA
mode: load, store, compare-and-swap) for std::atomic_uint in HCC.
the attached patch implements atomic compare and swap for SI+
(untested). I tried to stay within what was available, but there are
few issues that I was unsure how to address:
1.) it currently uses v2i32 for both input and output. This
2014 Mar 07
3
[LLVMdev] [RFC] Add second "failure" AtomicOrdering to cmpxchg instruction
...ry:
%newval.addr = alloca i32, align 4
store i32 %newval, i32* %newval.addr, align 4
%tmp = load i32* %newval.addr, align 4
- %0 = cmpxchg i32* @x, i32 %oldval, i32 %tmp monotonic
+ %0 = cmpxchg i32* @x, i32 %oldval, i32 %tmp monotonic monotonic
ret i32 %0
; CHECK-EL-LABEL: AtomicCmpSwap32:
@@ -333,7 +333,7 @@ entry:
define signext i8 @AtomicCmpSwap8(i8 signext %oldval, i8 signext %newval) nounwind {
entry:
- %0 = cmpxchg i8* @y, i8 %oldval, i8 %newval monotonic
+ %0 = cmpxchg i8* @y, i8 %oldval, i8 %newval monotonic monotonic
ret i8 %0
; CHECK-EL-LABEL: AtomicCmpSwap...