Displaying 15 results from an estimated 15 matches for "cmp7".
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2016 May 27
2
Handling post-inc users in LSR
...mined. Luckily, I was able to remove the
redundant add instruction with this hack, but I really doubt if it
make sense to prevent a loop terminating condition from being changed to
postinc form when it's already a post-inc user.
# Input IR :
define void @foo(i32 %n, i32* %P) {
entry:
%cmp7 = icmp sgt i32 %n, 1
br i1 %cmp7, label %for.body.preheader, label %for.end
for.body.preheader: ; preds = %entry
%n_sext = sext i32 %n to i64
br label %for.body
for.body:
%K.in = phi i64 [ %n_sext, %for.body.preheader ], [ %K, %for.body ]
%K = add i64...
2016 May 27
0
Handling post-inc users in LSR
...loop terminating condition from being changed to postinc form when it's already a post-inc user.
I agree, but don’t have a better suggestion. You could file a bug. Anyone have time to try out some fixes?
Andy
> # Input IR :
>
> define void @foo(i32 %n, i32* %P) {
> entry:
> %cmp7 = icmp sgt i32 %n, 1
> br i1 %cmp7, label %for.body.preheader, label %for.end
>
> for.body.preheader: ; preds = %entry
> %n_sext = sext i32 %n to i64
> br label %for.body
>
> for.body:
> %K.in = phi i64 [ %n_sext, %for.body.preheader ], [...
2015 Sep 28
4
varargs, the x86, and clang
...-64,
versus the varargs stuff I was led to expect from the LLVM IR documentation.
define i32 @add_em_up(i32 %count, ...) #0 {
entry:
%ap = alloca [1 x %struct.__va_list_tag], align 16
%arraydecay1 = bitcast [1 x %struct.__va_list_tag]* %ap to i8*
call void @llvm.va_start(i8* %arraydecay1)
%cmp7 = icmp sgt i32 %count, 0
br i1 %cmp7, label %for.body.lr.ph, label %for.end
for.body.lr.ph: ; preds = %entry
%gp_offset_p = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap,
i64 0, i64 0, i32 0
%0 = getelementptr inbounds [1 x %struct.__va_list_tag]*...
2017 Dec 19
4
MemorySSA question
...v35
*; 1 = MemoryDef(3)*
store i32 %add, i32* %arrayidx4, align 4, !tbaa !2
%indvars.iv.next36 = add nuw nsw i64 %indvars.iv35, 5
%cmp = icmp slt i64 %indvars.iv.next36, %1
br i1 %cmp, label %for.body, label %for.end
for.end: ; preds = %for.body
%cmp729 = icmp sgt i32 %0, 5
br i1 %cmp729, label %for.body8.lr.ph, label %for.end17
for.body8.lr.ph: ; preds = %for.end
%sub = add nsw i32 %0, -5
%4 = sext i32 %sub to i64
br label %for.body8
for.body8: ; preds = %
for.b...
2017 Dec 19
2
MemorySSA question
...yidx4, align 4, !tbaa !2
>> %indvars.iv.next36 = add nuw nsw i64 %indvars.iv35, 5
>> %cmp = icmp slt i64 %indvars.iv.next36, %1
>> br i1 %cmp, label %for.body, label %for.end
>>
>> for.end: ; preds = %for.body
>> %cmp729 = icmp sgt i32 %0, 5
>> br i1 %cmp729, label %for.body8.lr.ph, label %for.end17
>>
>> for.body8.lr.ph: ; preds = %for.end
>> %sub = add nsw i32 %0, -5
>> %4 = sext i32 %sub to i64
>> br label %for.body8
>>
>>...
2017 Sep 14
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...ne <2 x i32> %vecinit1, <i32 0, i32 -23>
%1 = extractelement <2 x i1> %0, i32 %i.022
%vecext4 = extractelement <2 x i32> %vecinit1, i32 %i.022
%vecext5 = extractelement <2 x i32> <i32 0, i32 -23>, i32 %i.022
%cmp6 = icmp ne i32 %vecext4, %vecext5
%cmp7 = xor i1 %1, %cmp6
...
and the SelectionDAG before TypeLegalizer is like this.
t0: ch = EntryToken
t2: i32,ch = CopyFromReg t0, Register:i32 %vreg0
t3: ch = ValueType:i32
t5: i32,ch = CopyFromReg t2:1, Register:i32 %vreg1
t7: i32 = AssertZext t5, ValueType:ch:i1
t8: v2i32...
2017 May 19
4
memcmp code fragment
...rayidx, align 1
%idxprom1 = zext i32 %i2 to i64
%arrayidx2 = getelementptr inbounds i8, i8* %block, i64 %idxprom1
%1 = load i8, i8* %arrayidx2, align 1
%cmp = icmp eq i8 %0, %1
br i1 %cmp, label %if.end, label %if.then
if.then: ; preds = %entry
%cmp7 = icmp ugt i8 %0, %1
br label %return
if.end: ; preds = %entry
%inc = add i32 %i1, 1
%inc10 = add i32 %i2, 1
%idxprom11 = zext i32 %inc to i64
%arrayidx12 = getelementptr inbounds i8, i8* %block, i64 %idxprom11
%2 = load i8, i8* %arrayidx12, al...
2018 May 16
0
GlobalAddress lowering strategy
...6, label %if.then5
if.then5: ; preds = %if.end3
tail call void @abort() #3
unreachable
if.end6: ; preds = %if.end3
%3 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]*
@a, i32 0, i32 3), align 4
%cmp7 = icmp eq i32 %3, 1
br i1 %cmp7, label %if.end9, label %if.then8
if.then8: ; preds = %if.end6
tail call void @abort() #3
unreachable
if.end9: ; preds = %if.end6
tail call void @exit(i32 0) #3
unreachable
}...
2017 Sep 15
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...%vecinit1, <i32 0, i32 -23>
> %1 = extractelement <2 x i1> %0, i32 %i.022
> %vecext4 = extractelement <2 x i32> %vecinit1, i32 %i.022
> %vecext5 = extractelement <2 x i32> <i32 0, i32 -23>, i32 %i.022
> %cmp6 = icmp ne i32 %vecext4, %vecext5
> %cmp7 = xor i1 %1, %cmp6
>
> ...
>
> and the SelectionDAG before TypeLegalizer is like this.
>
> t0: ch = EntryToken
> t2: i32,ch = CopyFromReg t0, Register:i32 %vreg0
> t3: ch = ValueType:i32
> t5: i32,ch = CopyFromReg t2:1, Register:i32 %vreg1
> t7: i32 = A...
2017 Sep 17
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...ne <2 x i32> %vecinit1, <i32 0, i32 -23>
%1 = extractelement <2 x i1> %0, i32 %i.022
%vecext4 = extractelement <2 x i32> %vecinit1, i32 %i.022
%vecext5 = extractelement <2 x i32> <i32 0, i32 -23>, i32 %i.022
%cmp6 = icmp ne i32 %vecext4, %vecext5
%cmp7 = xor i1 %1, %cmp6
...
and the SelectionDAG before TypeLegalizer is like this.
t0: ch = EntryToken
t2: i32,ch = CopyFromReg t0, Register:i32 %vreg0
t3: ch = ValueType:i32
t5: i32,ch = CopyFromReg t2:1, Register:i32 %vreg1
t7: i32 = AssertZext t5, ValueType:ch:i1
t8:...
2017 Sep 18
1
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...ne <2 x i32> %vecinit1, <i32 0, i32 -23>
%1 = extractelement <2 x i1> %0, i32 %i.022
%vecext4 = extractelement <2 x i32> %vecinit1, i32 %i.022
%vecext5 = extractelement <2 x i32> <i32 0, i32 -23>, i32 %i.022
%cmp6 = icmp ne i32 %vecext4, %vecext5
%cmp7 = xor i1 %1, %cmp6
...
and the SelectionDAG before TypeLegalizer is like this.
t0: ch = EntryToken
t2: i32,ch = CopyFromReg t0, Register:i32 %vreg0
t3: ch = ValueType:i32
t5: i32,ch = CopyFromReg t2:1, Register:i32 %vreg1
t7: i32 = AssertZext t5, ValueType:ch:i1
t8:...
2012 Oct 18
0
[LLVMdev] Debugging LLVM IR with GDB
> Has anybody debugged LLVM IR with GDB? I'm using dragonegg to transform C
> into IR, then applying my optimizations. Passing "-g" to dragonegg doesn't
> seem to work since it generates debug info for the C code, not the IR. I
> really need GDB (lli doesn't solve my problems) in order to debug
> multi-threaded and multi-process MPI code.
>
> More
2012 Oct 18
4
[LLVMdev] Debugging LLVM IR with GDB
...%and.i.i.i.i85 = and i64 %7, 70368744177660
(gdb) n
14 while(j++ < i) k += j;
(gdb) n
11 while(i-- > argc)
(gdb) n
14 while(j++ < i) k += j;
(gdb) n
102 %77 = load i8** @global, align 8
(gdb) n
105 %79 = load i32* %78, align 4
(gdb) n
106 %cmp7.i.i.i = icmp ne i32 %79, 0
(gdb) n
108 call void @llvm.memset.p0i8.i64(i8* %add.ptr.i.i.i.i86, i8
%conv8.i.i.i, i64 4, i32 1, i1 false) nounwind
(gdb) n
14 while(j++ < i) k += j;
(gdb) n
15 while(j-- > 0) k *= k + j;
(gdb) n
95 %69 = load i8** @global, align 8
(...
2012 Oct 17
5
[LLVMdev] Debugging LLVM IR with GDB
Hi all,
Has anybody debugged LLVM IR with GDB? I'm using dragonegg to transform
C into IR, then applying my optimizations. Passing "-g" to dragonegg
doesn't seem to work since it generates debug info for the C code, not
the IR. I really need GDB (lli doesn't solve my problems) in order to
debug multi-threaded and multi-process MPI code.
More clearly, if I have a file
2013 Feb 14
1
[LLVMdev] LiveIntervals analysis problem
...; preds = %for.cond66.i
%arrayidx70.i = getelementptr inbounds [13 x i16]* %t.i, i32 0, i32 %j.0.i
%217 = load i16* %arrayidx70.i, align 2, !tbaa !5
%arrayidx72.i = getelementptr inbounds [13 x i16]* %w.i, i32 0, i32 %j.0.i
%218 = load i16* %arrayidx72.i, align 2, !tbaa !5
%cmp74.i = icmp eq i16 %217, %218
%inc79.i = add nsw i32 %j.0.i, 1
br i1 %cmp74.i, label %for.cond66.i, label %noint.i
for.end80.i: ; preds = %for.cond66.i
%219 = load i16* %arraydecay12.i, align 2, !tbaa !5
store i16 %219, i16* %arraydecay60.i, align 2, !tba...