search for: cmp

Displaying 20 results from an estimated 1824 matches for "cmp".

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2006 Aug 12
4
Several files's checksum change without reason
..."rpm -Va" command does not output md5sum change for those files. compare time: Sat Aug 12 05:35:14 2006 host: server scan config: server (abcdefg) log file: no log file generated, see system log. base database: 56 compare database: 57 [211][server][cmp][/usr/bin][mtime][Sun Aug 6 04:02:20 2006][Sat Aug 12 04:02:22 2006] [213][server][cmp][/usr/bin][ctime][Sun Aug 6 04:02:20 2006][Sat Aug 12 04:02:22 2006] [204][server][cmp][/usr/bin/afs5log][checksum][b838bb6106250fdfd95ae8a7dc7fa95b8f762df4][a4c817dd8ca12449dc1a8bdf...
2006 May 31
5
Help with sorting arrays with objects in it
I have to build an array through both activerecord and also through a ferret index. I was hoping to find a way of sorting the array as i combine the two so def advanced_search(search_text, store, format, sortby) # find items in ferret index items = Item.find_by_contents(search_text) # and now find all the items from a certain store or category items_from_sql = Item.find_by_sql("SELECT *
2019 Jun 01
2
Optimizing Compare instruction selection
I attempt to optimize the use of the ‘CMP’ instruction on my architecture by removing the instruction instances where the Status Register already had the correct status flags. The cmp instruction in my architecture is the typical one that compares two registers, or a register with an immediate, and sets the Status Flags accordingly. I imp...
2015 Feb 05
3
[LLVMdev] Proposal for Poison Semantics
...hand it tells us what happens for > real codes which Alive does not. Turns out that undef + fast math flags is enough to cause LLVM to become inconsistent: define i1 @f(i1 %a.is_nan, float %a, float %b) { %add = fadd nnan float %a, %b %sel = select i1 %a.is_nan, float undef, float %add %cmp = fcmp ord float %b, %sel ret i1 %cmp } When 'b' is NaN, the following occurs: %add = float undef %sel = float undef %cmp = i1 false However, the 'select i1 %A, %B, undef' -> 'undef' optimization permits us to transform @f to: define i1 @f(i1 %a.is_nan, float %a, floa...
2015 Feb 13
2
[LLVMdev] trunk's optimizer generates slower code than 3.5
...ptr -40h var_34 = dword ptr -34h push rbp push r15 push r14 push r13 push r12 push rbx sub rsp, 18h mov ebx, 0FFFFFFFFh cmp edi, 2 jnz loc_100000F29 mov rdi, [rsi+8] ; char * xor r14d, r14d xor esi, esi ; char ** mov edx, 0Ah ; int call _strtol mov r15, rax...
2015 Feb 14
2
[LLVMdev] trunk's optimizer generates slower code than 3.5
...gt;> push r15 >> push r14 >> push r13 >> push r12 >> push rbx >> sub rsp, 18h >> mov ebx, 0FFFFFFFFh >> cmp edi, 2 >> jnz loc_100000F29 >> mov rdi, [rsi+8] ; char * >> xor r14d, r14d >> xor esi, esi ; char ** >> mov edx, 0Ah ; int >>...
2019 Jun 02
2
Optimizing Compare instruction selection
...even before I added the referred optimisations. The code that causes the problem is this: int doSmth( int y ); int test( int y ) { int neg = y < 0; if ( neg ) y = - y; int rv = doSmth( y ); return neg ? - rv : rv; } Apparently, LLVM attempts to physically use the result of a CMP instruction through a function call by storing it on a temporary register. This is found before the doSmth function call, t30: i16 = CMPkr16 t4, TargetConstant:i16<0> t36: ch,glue = CopyToReg t0, Register:i16 $sr, t30 t32: i16 = NEGSETCC TargetConstant:i16<4>, t36:1 And this...
2015 Feb 14
2
[LLVMdev] trunk's optimizer generates slower code than 3.5
...push r14 >>>> push r13 >>>> push r12 >>>> push rbx >>>> sub rsp, 18h >>>> mov ebx, 0FFFFFFFFh >>>> cmp edi, 2 >>>> jnz loc_100000F29 >>>> mov rdi, [rsi+8] ; char * >>>> xor r14d, r14d >>>> xor esi, esi ; char ** >>>> mov edx, 0A...
2015 May 09
2
[PATCH 3/4] nvc0/ir: optimize set & 1.0 to produce boolean-float sets
.../nv50_ir_peephole.cpp > +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp > @@ -973,6 +973,35 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s) > } > break; > > + case OP_AND: > + { > + CmpInstruction *cmp = i->getSrc(t)->getInsn()->asCmp(); > + if (!cmp || cmp->op == OP_SLCT) how about if (cmp == NULL || ...) and kill the same condition later? > + return; > + if (!prog->getTarget()->isOpSupported(cmp->op, TYPE_F32)) > + ret...
2014 Mar 07
3
[LLVMdev] [RFC] Add second "failure" AtomicOrdering to cmpxchg instruction
Hi all, The C++11 (& C11) compare_exchange functions with explicit memory order allow you to specify two sets of semantics, one for when the exchange actually happens and one for when it fails. Unfortunately, at the moment the LLVM IR "cmpxchg" instruction only has one ordering, which means we get sub-optimal codegen. This probably affects all architectures which use load-linked/store-conditional instructions for atomic operations and don't have versions with built-in acquire/release semantics (and so need barriers)...
2019 Jun 05
2
Optimizing Compare instruction selection
...em is this: > > int doSmth( int y ); > > int test( int y ) > { > int neg = y < 0; > if ( neg ) > y = - y; > > int rv = doSmth( y ); > > return neg ? - rv : rv; > } > > Apparently, LLVM attempts to physically use the result of a CMP instruction through a function call by storing it on a temporary register. This is found before the doSmth function call, > > t30: i16 = CMPkr16 t4, TargetConstant:i16<0> > t36: ch,glue = CopyToReg t0, Register:i16 $sr, t30 > t32: i16 = NEGSETCC TargetConstant:i16<4&...
2015 Feb 08
11
[LLVMdev] RFC: Proposal to Remove Poison
...We rely on the following properties for poison: - Instructions which have poison operands are capable of providing results which are not consistent with a two's complement operand. Here is a case where we believed distinguishing between poison and undef is essential: %add = add nsw i32 %a, %b %cmp = icmp sgt i32 %add, %a If %a is INT_MAX and %b is 1, then %add results in overflow. If overflow results in undef, then %cmp would be equivalent to: %cmp = icmp sgt i32 undef, INT_MIN There is no bit-pattern we could substitute for undef which would make %cmp true, this means that we cannot optim...
2011 Jun 01
4
[LLVMdev] AVX Status?
...ody (e.g. at Cray?) still actively working on it? I have tried both LLVM 2.9 final and the latest trunk, and it seems like some trivial stuff is already working and produces nice code for code using <8 x float>. Unfortunately, the backend gets confused about mask code as e.g. produced by VCMPPS together with mask operations (which LLVM requires to work on <8 x i32> atm) and corresponding bitcasts. Consider these two examples: define <8 x float> @test1(<8 x float> %a, <8 x float> %b, <8 x i32> %m) nounwind readnone { entry: %cmp = tail call <8 x fl...
2016 Nov 07
5
should we have IR intrinsics for integer min/max?
...tion may help to resolve larger questions about intrinsics and vectorization that were discussed at the dev mtg last week, but let's start with the basics: Which, if any, of these is the canonical IR? ; ret = x < y ? 0 : x-y define i32 @max1(i32 %x, i32 %y) { %sub = sub nsw i32 %x, %y %cmp = icmp slt i32 %x, %y ; cmp is independent of sub %sel = select i1 %cmp, i32 0, i32 %sub ret i32 %sel } ; ret = (x-y) < 0 ? 0 : x-y define i32 @max2(i32 %x, i32 %y) { %sub = sub nsw i32 %x, %y %cmp = icmp slt i32 %sub, 0 ; cmp depends on sub, but this looks more like a max? %sel = sel...
2016 Mar 10
2
[CodeGen] PeepholeOptimizer: optimizing condition dependent instrunctions
...to account that the instruction next to the current processed instruction must never be erased because this invalidates iterator. I've been fixing a bug in AArch64InstrInfo::optimizeCompareInstr: instructions are converted into S form but it's not checked that they produce the same flags as CMP. The bug exists upstream as well. Together with the fix I want to add some peephole rules for combinations CMP+BRC and CMP+SEL. In the context of optimizeCmpInstr I have all information about CmpInstr. I simply go down and check all instructions which use AArch64::NZCV whether they can be substitut...
2018 Jul 03
4
Question about canonicalizing cmp+select
Hi, Sanjay/all, I noticed in rL331486 that some compare-select optimizations are disabled in favor of providing canonicalized cmp+select to the backend. I am currently working on a private backend target, and the target has a small code size limit. With this change, some of the apps went over the codesize limit. As an example, C code: b = (a > -1) ? 4 : 5; ll code: Before rL331486: %0 = lshr i16 %a.0.a.0., 15...
2013 Apr 23
2
[LLVMdev] 'loop invariant code motion' and 'Reassociate Expression'
...[ %buf.0, %if.end ], [ %4, %sw.bb23 ], [ %3, %sw.bb18 ], [ %2, %sw.bb13 ], [ %1, %sw.bb ] %seed.addr.0 = phi i16 [ %seed, %entry ], [ %inc9, %if.end ], [ %inc9, %sw.bb23 ], [ %inc9, %sw.bb18 ], [ %inc9, %sw.bb13 ], [ %inc9, %sw.bb ] %add = add i32 %total.0, %next.0 %add1 = add i32 %add, 1 %cmp = icmp ult i32 %add1, %dec br i1 %cmp, label %while.body, label %while.cond29 *** IR Dump After Reassociate expressions *** define void @foo(i32 %size, i16 signext %seed, i8* nocapture %p) nounwind { entry: %dec = add i32 %size, -1 br label %while.cond while.cond:...
2016 Nov 08
2
should we have IR intrinsics for integer min/max?
...bout > intrinsics and vectorization that were discussed at the dev mtg last week, > but let's start with the basics: > > Which, if any, of these is the canonical IR? > > ; ret = x < y ? 0 : x-y > define i32 @max1(i32 %x, i32 %y) { > %sub = sub nsw i32 %x, %y > %cmp = icmp slt i32 %x, %y ; cmp is independent of sub > %sel = select i1 %cmp, i32 0, i32 %sub > ret i32 %sel > } > > ; ret = (x-y) < 0 ? 0 : x-y > define i32 @max2(i32 %x, i32 %y) { > %sub = sub nsw i32 %x, %y > %cmp = icmp slt i32 %sub, 0 ; cmp depends on sub, but t...
2017 Jul 13
2
failing to optimize boolean ops on cmps
...ptimizations in InstCombine for bitwise logic ops (and/or/xor) that fail to handle compare patterns with the equivalent bitwise logic. Example: define i8 @or_and_not(i8 %a, i8 %b) { %nota = xor i8 %a, -1 %and = and i8 %nota, %b %res = or i8 %and, %a ret i8 %res } define i1 @or_and_cmp_not(i32 %a, i32 %b, i1 %c) { %cmp = icmp sgt i32 %a, %b %cmp_inv = icmp sle i32 %a, %b ; this is 'not' of %cmp %and = and i1 %c, %cmp_inv %res = or i1 %cmp, %and ret i1 %res } $ ./opt -instcombine hidden_not.ll -S define i8 @or_and_not(i8 %a, i8 %b) { %res = or i8 %b, %a...
2014 Sep 02
2
[LLVMdev] Preserving NSW/NUW bits
...estion about NSW/NUW bits, if you've got a second. I noticed you've been doing a little work on this as of late. I have a bit of code that looks like the following: %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 %2 = add i64 %indvars.iv.next, -1 %tmp = trunc i64 %2 to i32 %cmp = icmp slt i32 %tmp, %0 br i1 %cmp, label %for.body, label %for.end.loopexit I'm trying to fold the 2nd add instruction into the compare by changing the condition from from 'slt' to 'sle': %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 %tmp = trunc i64 %indvars.iv.nex...