Displaying 20 results from an estimated 194 matches for "chiens".
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chien
2013 May 02
2
[LLVMdev] int to StringRed conversion
I think the better solution should be:
LLVMContext& C = is->getContext();
Value *values[] = {
ConstantInt::getSigned(Type::getInt64Ty(C), *scsr*),
MDString::get(C, *"path"*)
};
lnstr.setMetadata(*"your_analysis_name"*, MDNode::get(C, values));
So that you can take advantage of the type system of LLVM bitcode, and
don't have to cast the integers from/to strings
2013 May 02
0
[LLVMdev] int to StringRed conversion
Yes, it sounds good. I can try tomorrow.
Thank you for your advice !
On Thu, May 2, 2013 at 5:43 PM, Logan Chien <tzuhsiang.chien at gmail.com>wrote:
> I think the better solution should be:
>
>
> LLVMContext& C = is->getContext();
> Value *values[] = {
> ConstantInt::getSigned(Type::getInt64Ty(C), *scsr*),
> MDString::get(C, *"path"*)
> };
2013 Aug 21
1
[LLVMdev] Broken PLT on ARM from R183966
That change seems to fix things here. Thanks!
-Gordon
From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of JF Bastien
Sent: Wednesday, August 21, 2013 12:53 PM
To: Logan Chien
Cc: llvmdev at cs.uiuc.edu
Subject: Re: [LLVMdev] Broken PLT on ARM from R183966
I'm not very familiar with relocations but your fix looks the same as
2013 Aug 21
0
[LLVMdev] Broken PLT on ARM from R183966
I'm not very familiar with relocations but your fix looks the same
as ARMTargetLowering::LowerCall, so from that perspective it lgtm (but I
may be missing something).
On Wed, Aug 21, 2013 at 8:04 AM, Logan Chien <tzuhsiang.chien at gmail.com>wrote:
> Hi Anton and JF,
>
> Thanks for your review. After reading the source code more carefully, I
> have come up with a
2013 Aug 21
2
[LLVMdev] Broken PLT on ARM from R183966
Hi Anton and JF,
Thanks for your review. After reading the source code more carefully, I
have come up with a different way fix this issue. We can simply resolve
this issue by adding ARMII::MO_PLT flags with MachineInstrBuilder in
FastISel pass (without failing back to DAG lowering).
The new patch is attached, and the test case is not changed. Sorry for
your inconvenience. Please have a
2013 May 02
0
[LLVMdev] int to StringRed conversion
The problem is that I want to pass only srsr which is an int. "marked" was
just an example :)
Thanks you!
On Thu, May 2, 2013 at 5:06 PM, Logan Chien <tzuhsiang.chien at gmail.com>wrote:
> I'm not familiar with this, but maybe you can try:
>
> StringRef tst = ("marked" + Twine(srsr)).str();
>
> It seems that you can't use integer as meta data
2014 May 12
3
[LLVMdev] Libc++abi tests on ARM
On 12 May 2014 20:20, Logan Chien <tzuhsiang.chien at gmail.com> wrote:
> There is a known issue in the code generated by LLVM.
> As a workaround, I am adding "-funwind-tables" to compile the unit tests.
I thought I had fixed all of them. Do you have a bug number?
> BTW, the LLVM revision which I am using is r207501.
> It seems that the recent master has come
2014 Mar 15
2
[LLVMdev] EHABI: Remaining issues
On 15 March 2014 17:06, Logan Chien <tzuhsiang.chien at gmail.com> wrote:
> I would like to know what do you mean by "commoning them up"?
Hi Logan,
That'd be reducing ARM directives in favour of CFI, but as I said (and
you too), GNU compatibility will probably be an issue for a very long
time.
> For the space issue, I personally don't think this is a big issue.
2013 May 02
4
[LLVMdev] int to StringRed conversion
Hello everyone,
I have an integer and I want to convert it to StringRef in order to set
metadata.
setMetadata->(StringRef, MDNode*);
It is there a native LLVM way to do it?
1. In the llvm::APSInt Class is toString() method, which seems it is not
for this purpose
2. itoa and string are not part of LLVM
3. stringstream is not part of LLVM
4. to_string is not part of LLVM
5. any casting method?
2005 Sep 05
3
[LLVMdev] dependence analyzer for machine code?
why there is no general dependency analysis for the "machin code"?
perhaps it's because the instruction scheduling is only implemented
for sparcv9?
i am going to implement a dependency analysis pass for machine code
block. the result will be returned in a boost graph
(http://www.boost.org/libs/graph/doc/table_of_contents.html).
just to check if it has already been implemented. it
2005 Sep 22
3
[LLVMdev] name collision - llvm::tie and boost::tie
The BGL (Boost Graph Library) defines tie(), which is exactly what the
tie() defined in STLExtras.h.
The header files of GBL use boost::tie(), and other boost libraries
use boost::tie() too.
How to resolve the ambiguity for compiler?
--
Tzu-Chien Chiu,
3D Graphics Hardware Architect
<URL:http://www.csie.nctu.edu.tw/~jwchiu>
2014 Feb 21
3
[LLVMdev] Status of http://llvm.org/doxygen
Hi,
I found that http://llvm.org/doxygen seems to be out-of-date. The footer
shows that the files are regenerated everyday. I guess that the input
repository for doxygen has not been updated for a while.
For example,
http://llvm.org/doxygen/namespacellvm.html#adeb6bbe8b1bed333ee7608e1939153c0
It says llvm::ParseBitcodeFile() has following prototype:
Module *ParseBitcodeFile(MemoryBuffer
2005 Sep 07
4
[LLVMdev] LiveIntervals, replace register with representative register?
I don't understand the following code snippet in LiveIntervalAnalysis.cpp.
Why changing the type of the opreand from a virtual register to a
machine register? The register number (reg) is still a virtual
register index (>1024).
bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
// perform a final pass over the instructions and compute spill
// weights, coalesce
2005 Jul 26
1
[LLVMdev] How to partition registers into different RegisterClass?
2005/7/26, Chris Lattner <sabre at nondot.org>:
> Tzu-Chien Chiu wrote:
> > The same problem exists when there are two types of costant registers,
> > floating point and integer, and each is declared 'packed' ([4xfloat]
> > and [4xint]). The instruction selector doesn't know which instruction
> > it should produce because the newly defined MVT type
2005 Sep 05
2
[LLVMdev] Pass is not automatically registered
I am not sure if my problem is similar to:
http://lists.cs.uiuc.edu/pipermail/llvmdev/2003-December/000715.html
It seems that the constructor of the static global pass object isn't called:
lib/CodeGen/DependenceAnalyzer.cpp:
static RegisterAnalysis<DependenceAnalyzer> X("depana", "Dependence Analysis");
I traced into struct RegisterAnalysis ctor, but my pass
2005 Apr 24
2
[LLVMdev] trig language-like code generator generator
http://portal.acm.org/citation.cfm?id=75700
On 4/25/05, Chris Lattner <sabre at nondot.org> wrote:
> On Sun, 24 Apr 2005, Tzu-Chien Chiu wrote:
> > i'd like to know if there is any plan or existing work to add a Aho's
> > trig language like code generator generator?
>
> Trig is a code generator generator? Is there any documentation for it
> available
2005 Jul 27
3
[LLVMdev] How to define complicated instruction in TableGen (Direct3D shader instruction)
Each register is a 4-component (namely, r, g, b, a) vector register.
They are actually defined as llvm packed [4xfloat].
The instruction:
add_sat r0.a, r1_bias.xxyy, r3_x2.zzzz
Explaination:
'.a' is a writemask. only the specified component will be update
'.xxyy' and '.zzzz' are swizzle masks, specify the component
permutation, simliar to the Intel SSE permutation
2005 Sep 07
3
[LLVMdev] LiveIntervals invalidates LiveVariables?
I though LiveVariables may be invalidated by LiveIntervals, but it's
declared not:
void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const
{
AU.addPreserved<LiveVariables>();
AU.addRequired<LiveVariables>();
...
LiveInterval may coalesce virtual registers and remove identity moves
instructions:
bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
2005 Jul 29
0
[LLVMdev] How to define complicated instruction in TableGen (Direct3D shader instruction)
Actually the problems that Tzu-Chien Chiu are encountering are similar to what should be done for generating SSE code in
the X86 backend and also other SIMD instruction sets. I think LLVM neeeds to add instructions for permuting components,
extracting and injecting elements in packed types. If the architecture has instructions which can do permutations for
each instruction (for example
2014 Mar 21
2
[LLVMdev] Unwind, exception handling, debuggers and profilers
On 21 March 2014 18:47, Logan Chien <tzuhsiang.chien at gmail.com> wrote:
> * There's the table for ARM target:
>
> - no attribute => emit unwind table
> - with nounwind => emit unwind table with cantunwind
> - with uwtable => emit unwind table
> - with uwtable+nounwind => emit unwind table WITHOUT the cantunwind
>
> The cantunwind record will stop the