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...hu, May 2, 2013 at 11:10 PM, Alexandru Ionut Diaconescu < alexandruionutdiaconescu at gmail.com> wrote: > The problem is that I want to pass only srsr which is an int. "marked" was > just an example :) > > Thanks you! > > > On Thu, May 2, 2013 at 5:06 PM, Logan Chien <tzuhsiang.chien at gmail.com>wrote: > >> I'm not familiar with this, but maybe you can try: >> >> StringRef tst = ("marked" + Twine(srsr)).str(); >> >> It seems that you can't use integer as meta data kind name. >> >> Logan >&...

Yes, it sounds good. I can try tomorrow. Thank you for your advice ! On Thu, May 2, 2013 at 5:43 PM, Logan Chien <tzuhsiang.chien at gmail.com>wrote: > I think the better solution should be: > > > LLVMContext& C = is->getContext(); > Value *values[] = { > ConstantInt::getSigned(Type::getInt64Ty(C), *scsr*), > MDString::get(C, *"path"*) > }; > > lnstr.s...

That change seems to fix things here. Thanks! -Gordon From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of JF Bastien Sent: Wednesday, August 21, 2013 12:53 PM To: Logan Chien Cc: llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] Broken PLT on ARM from R183966 I'm not very familiar with relocations but your fix looks the same as ARMTargetLowering::LowerCall, so from that perspective it lgtm (but I may be missing something). On Wed, Aug 21, 2013 at 8:04 AM, Logan Chien...

I'm not very familiar with relocations but your fix looks the same as ARMTargetLowering::LowerCall, so from that perspective it lgtm (but I may be missing something). On Wed, Aug 21, 2013 at 8:04 AM, Logan Chien <tzuhsiang.chien at gmail.com>wrote: > Hi Anton and JF, > > Thanks for your review. After reading the source code more carefully, I > have come up with a different way fix this issue. We can simply resolve > this issue by adding ARMII::MO_PLT flags with MachineInstrBuilder...

...Sincerely, Logan On Wed, Aug 21, 2013 at 10:52 PM, JF Bastien <jfb at google.com> wrote: > lgtm > > > On Wed, Aug 21, 2013 at 3:18 AM, Anton Korobeynikov < > anton at korobeynikov.info> wrote: > >> LGTM >> >> On Wed, Aug 21, 2013 at 1:51 PM, Logan Chien <tzuhsiang.chien at gmail.com> >> wrote: >> > Hi, >> > >> > I have created a workaround to deal with the PIC function call. With >> this >> > patch, the FastISel will switch back to DAG lowering mechanism if (1) >> there >> > i...

The problem is that I want to pass only srsr which is an int. "marked" was just an example :) Thanks you! On Thu, May 2, 2013 at 5:06 PM, Logan Chien <tzuhsiang.chien at gmail.com>wrote: > I'm not familiar with this, but maybe you can try: > > StringRef tst = ("marked" + Twine(srsr)).str(); > > It seems that you can't use integer as meta data kind name. > > Logan > > > On Thu, May 2, 2013 at...

On 12 May 2014 20:20, Logan Chien <tzuhsiang.chien at gmail.com> wrote: > There is a known issue in the code generated by LLVM. > As a workaround, I am adding "-funwind-tables" to compile the unit tests. I thought I had fixed all of them. Do you have a bug number? > BTW, the LLVM revision which I am usin...

On 15 March 2014 17:06, Logan Chien <tzuhsiang.chien at gmail.com> wrote: > I would like to know what do you mean by "commoning them up"? Hi Logan, That'd be reducing ARM directives in favour of CFI, but as I said (and you too), GNU compatibility will probably be an issue for a very long time. > For the...

Hello everyone, I have an integer and I want to convert it to StringRef in order to set metadata. setMetadata->(StringRef, MDNode*); It is there a native LLVM way to do it? 1. In the llvm::APSInt Class is toString() method, which seems it is not for this purpose 2. itoa and string are not part of LLVM 3. stringstream is not part of LLVM 4. to_string is not part of LLVM 5. any casting method?

...o implement a dependency analysis pass for machine code block. the result will be returned in a boost graph (http://www.boost.org/libs/graph/doc/table_of_contents.html). just to check if it has already been implemented. it seems to be a very common used pass (for instruction scheduling). -- Tzu-Chien Chiu, 3D Graphics Hardware Architect <URL:http://www.csie.nctu.edu.tw/~jwchiu>

The BGL (Boost Graph Library) defines tie(), which is exactly what the tie() defined in STLExtras.h. The header files of GBL use boost::tie(), and other boost libraries use boost::tie() too. How to resolve the ambiguity for compiler? -- Tzu-Chien Chiu, 3D Graphics Hardware Architect <URL:http://www.csie.nctu.edu.tw/~jwchiu>

Hi, I found that http://llvm.org/doxygen seems to be out-of-date. The footer shows that the files are regenerated everyday. I guess that the input repository for doxygen has not been updated for a while. For example, http://llvm.org/doxygen/namespacellvm.html#adeb6bbe8b1bed333ee7608e1939153c0 It says llvm::ParseBitcodeFile() has following prototype: Module *ParseBitcodeFile(MemoryBuffer

...gister with representative register unsigned reg = rep(mop.getReg()); mii->SetMachineOperandReg(i, reg); LiveInterval &RegInt = getInterval(reg); RegInt.weight += (mop.isUse() + mop.isDef()) * pow(10.0F, (int)loopDepth); -- Tzu-Chien Chiu, 3D Graphics Hardware Architect <URL:http://www.csie.nctu.edu.tw/~jwchiu>

2005/7/26, Chris Lattner <sabre at nondot.org>: > Tzu-Chien Chiu wrote: > > The same problem exists when there are two types of costant registers, > > floating point and integer, and each is declared 'packed' ([4xfloat] > > and [4xint]). The instruction selector doesn't know which instruction > > it should produce because...

...isUsage(AU); } class RegAllocMultibank : public MachineFunctionPass { virtual void getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired<LiveIntervals>(); AU.addRequired<DependenceAnalyzer>(); MachineFunctionPass::getAnalysisUsage(AU); } }; -- Tzu-Chien Chiu, 3D Graphics Hardware Architect <URL:http://www.csie.nctu.edu.tw/~jwchiu>

http://portal.acm.org/citation.cfm?id=75700 On 4/25/05, Chris Lattner <sabre at nondot.org> wrote: > On Sun, 24 Apr 2005, Tzu-Chien Chiu wrote: > > i'd like to know if there is any plan or existing work to add a Aho's > > trig language like code generator generator? > > Trig is a code generator generator? Is there any documentation for it > available anywhere? > > -Chris > > > &qu...

...t it makes the implementing the instruction selector very diffifult. in this example, llvm.select() and llvm.sature() are encountered frist (bootm-up), but they must be 'remembered' and the instruction cannot be generated (BuildMI) until the opcode is known. Which one should I do? -- Tzu-Chien Chiu, 3D Graphics Hardware Architect <URL:http://www.csie.nctu.edu.tw/~jwchiu>

...... // perform a final pass over the instructions and compute spill // weights, coalesce virtual registers and remove identity moves but the data structure LiveVariables::VirtRegInfo is _not_ updated. That is, VarInfo::DefInstr may point to an invalid (being coalesced) instruction. -- Tzu-Chien Chiu, 3D Graphics Hardware Architect <URL:http://www.csie.nctu.edu.tw/~jwchiu>

Actually the problems that Tzu-Chien Chiu are encountering are similar to what should be done for generating SSE code in the X86 backend and also other SIMD instruction sets. I think LLVM neeeds to add instructions for permuting components, extracting and injecting elements in packed types. If the architecture has instructions which...

On 21 March 2014 18:47, Logan Chien <tzuhsiang.chien at gmail.com> wrote: > * There's the table for ARM target: > > - no attribute => emit unwind table > - with nounwind => emit unwind table with cantunwind > - with uwtable => emit unwind table > - with uwtable+nounwind => emit unwind table WIT...