search for: ccassigntostack

Hi Is there a way to enforce a different alignment on vales on stack as compared to other basic types. Particularly, i would like characters to be stored at 2 byte boundary. thanks dz

...k out examples in the lib/Target/* directories. For instance in X86CallingConv.td, we have things like this: def CC_X86_64_C : CallingConv<[ ... // __m64 vectors get 8-byte stack slots that are 8-byte aligned. CCIfType<[x86mmx,v1i64], CCAssignToStack<8, 8>> } The second parameter to CCAssigneToStack is the alignment for that type. -bw

...yte boundary. >> > Check out examples in the lib/Target/* directories. For instance in X86CallingConv.td, we have things like this: > > def CC_X86_64_C : CallingConv<[ > ... >  // __m64 vectors get 8-byte stack slots that are 8-byte aligned. >  CCIfType<[x86mmx,v1i64], CCAssignToStack<8, 8>> > } > > The second parameter to CCAssigneToStack is the alignment for that type. > > -bw > >

.../Target/X86/X86CallingConv.td (revision 164763) +++ lib/Target/X86/X86CallingConv.td (working copy) @@ -335,7 +335,8 @@ CCIfType<[i8, i16], CCPromoteToType<i32>>, // Pass sret arguments indirectly through EAX - CCIfSRet<CCAssignToReg<[EAX]>>, + CCIfSRet<CCAssignToStack<4, 4>>, // The first integer argument is passed in ECX CCIfType<[i32], CCAssignToReg<[ECX]>>, --------------------------------- [hope this doesn't get wrapped in your email client] Unfortunately, this patch also changes how SRet/ThisCall behaves non-Windows systems...

Hi, Dan > The goal of the patch is to eliminate a bunch of awkward code, > eliminate some unnecessary differences between targets, and to > facilitate future refactoring and feature work. I quickly looked over the patch and it seems to be a significant cleanup of all really ugly lowering code! Maybe it will be possible to provide some dummy implementation of LowerFormalArguments /

Attached is a working patch set for llvm to be able to emit arm64 (currently as triple aarch64-apple-ios) mach-o object files, in case someone is interested. I'm not sure if the llvm maintainers want the patch given the previous message that there's going to be an official patch set from apple to support this, but here is mine. What works (tested on an iPhone 5S): * objc strings,

...--------------------------------------------------------------===// def CC_DLX : CallingConv<[ // The first 6 arguments are passed in registers CCIfType<[i32], CCAssignToReg<[R1, R2, R3, R4, R5, R6]>>, // Stack slots are 4 bytes in size and 4-byte aligned. CCIfType<[i32], CCAssignToStack<4, 4>> ]>;

...we handled it > > Your change isn't handling the "NeededStackSize = 8" case. I believe it is. I've attached two additional test cases. The difference is that this case isn't handled by the CCCustomFns. They fail to allocate any regs and then handling falls through to an CCAssignToStack in ARMCallingConv.td. This is how other targets handle similar allocations. > ++ static const unsigned HiRegList[] = { ARM::R0, ARM::R2 }; > + static const unsigned LoRegList[] = { ARM::R1, ARM::R3 }; > + > + if (unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2)) { > +...

...Your change isn't handling the "NeededStackSize = 8" case. > > I believe it is. I've attached two additional test cases. The > difference is that this case isn't handled by the CCCustomFns. They > fail to allocate any regs and then handling falls through to an > CCAssignToStack in ARMCallingConv.td. This is how other targets handle > similar allocations. > >> ++ static const unsigned HiRegList[] = { ARM::R0, ARM::R2 }; >> + static const unsigned LoRegList[] = { ARM::R1, ARM::R3 }; >> + >> + if (unsigned Reg = State.AllocateReg(HiRegList, L...

...t handling the "NeededStackSize = 8" case. >> >> I believe it is. I've attached two additional test cases. The >> difference is that this case isn't handled by the CCCustomFns. They >> fail to allocate any regs and then handling falls through to an >> CCAssignToStack in ARMCallingConv.td. This is how other targets >> handle >> similar allocations. >> >>> ++ static const unsigned HiRegList[] = { ARM::R0, ARM::R2 }; >>> + static const unsigned LoRegList[] = { ARM::R1, ARM::R3 }; >>> + >>> + if (unsigned R...

...;NeededStackSize = 8" case. >>> >>> I believe it is. I've attached two additional test cases. The >>> difference is that this case isn't handled by the CCCustomFns. They >>> fail to allocate any regs and then handling falls through to an >>> CCAssignToStack in ARMCallingConv.td. This is how other targets >>> handle >>> similar allocations. >>> >>>> ++  static const unsigned HiRegList[] = { ARM::R0, ARM::R2 }; >>>> +  static const unsigned LoRegList[] = { ARM::R1, ARM::R3 }; >>>> + >>...

...gt;>> I believe it is. I've attached two additional test cases. The >>>>> difference is that this case isn't handled by the CCCustomFns. >>>>> They >>>>> fail to allocate any regs and then handling falls through to an >>>>> CCAssignToStack in ARMCallingConv.td. This is how other targets >>>>> handle >>>>> similar allocations. >>>>> >>>>>> ++ static const unsigned HiRegList[] = { ARM::R0, ARM::R2 }; >>>>>> + static const unsigned LoRegList[] = { ARM::R1...

..." case. >>>> >>>> I believe it is. I've attached two additional test cases. The >>>> difference is that this case isn't handled by the CCCustomFns. They >>>> fail to allocate any regs and then handling falls through to an >>>> CCAssignToStack in ARMCallingConv.td. This is how other targets >>>> handle >>>> similar allocations. >>>> >>>>> ++  static const unsigned HiRegList[] = { ARM::R0, ARM::R2 }; >>>>> +  static const unsigned LoRegList[] = { ARM::R1, ARM::R3 }; >&gt...

Thanks. More questions :-) /// Information about how the value is assigned. - LocInfo HTP : 7; + LocInfo HTP : 6; Do you know why this change is needed? Are we running out of bits? - NeededStackSize = 4; - break; - case MVT::i64: - case MVT::f64: - if (firstGPR < 3) - NeededGPRs = 2; - else if (firstGPR == 3) { - NeededGPRs = 1; - NeededStackSize = 4; -

...lieve it is. I've attached two additional test cases. The >>>>>> difference is that this case isn't handled by the CCCustomFns. >>>>>> They >>>>>> fail to allocate any regs and then handling falls through to an >>>>>> CCAssignToStack in ARMCallingConv.td. This is how other targets >>>>>> handle >>>>>> similar allocations. >>>>>> >>>>>>> ++ static const unsigned HiRegList[] = { ARM::R0, ARM::R2 }; >>>>>>> + static const unsigned LoR...

Hello, Attached is a patch which significantly reworks how calls, incoming arguments, and outgoing return values are lowered. It's a major change, affecting all targets, so I'm looking for feedback on the approach. The goal of the patch is to eliminate a bunch of awkward code, eliminate some unnecessary differences between targets, and to facilitate future refactoring and feature work.