search for: bus_addr

...proc->dev, "slim stopped\n"); + + return 0; +} + +static void *slim_rproc_da_to_va(struct rproc *rproc, u64 da, int len) +{ + struct st_slim_rproc *slim_rproc = rproc->priv; + void *va = NULL; + int i; + + for (i = 0; i < ST_SLIM_MEM_MAX; i++) { + if (da != slim_rproc->mem[i].bus_addr) + continue; + + if (len <= slim_rproc->mem[i].size) { + /* __force to make sparse happy with type conversion */ + va = (__force void *)slim_rproc->mem[i].cpu_addr; + break; + } + } + + dev_dbg(&rproc->dev, "%s: da = 0x%llx len = 0x%x va = 0x%p\n", + __func__, d...

...urn 0; > +} > + > +static void *slim_rproc_da_to_va(struct rproc *rproc, u64 da, int len) > +{ > + struct st_slim_rproc *slim_rproc = rproc->priv; > + void *va = NULL; > + int i; > + > + for (i = 0; i < ST_SLIM_MEM_MAX; i++) { > + if (da != slim_rproc->mem[i].bus_addr) > + continue; > + > + if (len <= slim_rproc->mem[i].size) { > + /* __force to make sparse happy with type conversion */ > + va = (__force void *)slim_rproc->mem[i].cpu_addr; > + break; > + } > + } > + > + dev_dbg(&rproc->dev, "%s: da = 0...

...urn 0; > +} > + > +static void *slim_rproc_da_to_va(struct rproc *rproc, u64 da, int len) > +{ > + struct st_slim_rproc *slim_rproc = rproc->priv; > + void *va = NULL; > + int i; > + > + for (i = 0; i < ST_SLIM_MEM_MAX; i++) { > + if (da != slim_rproc->mem[i].bus_addr) > + continue; > + > + if (len <= slim_rproc->mem[i].size) { > + /* __force to make sparse happy with type conversion */ > + va = (__force void *)slim_rproc->mem[i].cpu_addr; > + break; > + } > + } > + > + dev_dbg(&rproc->dev, "%s: da = 0...

...void *slim_rproc_da_to_va(struct rproc *rproc, u64 da, int len) > > +{ > > + struct st_slim_rproc *slim_rproc = rproc->priv; > > + void *va = NULL; > > + int i; > > + > > + for (i = 0; i < ST_SLIM_MEM_MAX; i++) { > > + if (da != slim_rproc->mem[i].bus_addr) > > + continue; > > + > > + if (len <= slim_rproc->mem[i].size) { > > + /* __force to make sparse happy with type conversion */ > > + va = (__force void *)slim_rproc->mem[i].cpu_addr; > > + break; > > + } > > + } > > + > &...

Convert the AMD iommu driver to the dma-iommu api. Remove the iova handling and reserve region code from the AMD iommu driver. Change-log: V6: -add more details to the description of patch 001-iommu-amd-Remove-unnecessary-locking-from-AMD-iommu-.patch -rename handle_deferred_device to iommu_dma_deferred_attach -fix double tabs in 0003-iommu-dma-iommu-Handle-deferred-devices.patch V5: -Rebase on

Convert the AMD iommu driver to the dma-iommu api. Remove the iova handling and reserve region code from the AMD iommu driver. Change-log: V4: -Rebase on top of linux-next -Split the removing of the unnecessary locking in the amd iommu driver into a seperate patch -refactor the "iommu/dma-iommu: Handle deferred devices" patch and address comments v3: -rename dma_limit to dma_mask -exit

Convert the AMD iommu driver to the dma-iommu api. Remove the iova handling and reserve region code from the AMD iommu driver. Change-log: V4: -Rebase on top of linux-next -Split the removing of the unnecessary locking in the amd iommu driver into a seperate patch -refactor the "iommu/dma-iommu: Handle deferred devices" patch and address comments v3: -rename dma_limit to dma_mask -exit

...c:6a fwe0: Ethernet address: 02:0d:9d:43:0c:6a fwip0: <IP over FireWire> on firewire0 fwip0: Firewire address: 00:0d:9d:71:9e:43:0c:6a @ 0xfffe00000000, S400, maxrec 2048 sbp0: <SBP-2/SCSI over FireWire> on firewire0 dcons_crom0: <dcons configuration ROM> on firewire0 dcons_crom0: bus_addr 0x12bc000 fwohci0: Initiate bus reset fwohci0: BUS reset fwohci0: node_id=0xc000ffc0, gen=1, CYCLEMASTER mode atapci0: <AcerLabs M5229 UDMA100 controller> port 0x1f0-0x1f7,0x3f6,0x170-0x177,0x376,0x8080-0x808f at device 16.0 on pci0 atapci0: using PIO transfers above 137GB as workaround for 4...

Hi Vinod, Bjorn, Patrice, This patchset adds support for the Flexible Direct Memory Access (FDMA) core found on STi chipsets from STMicroelectronics. The FDMA is a slim core CPU with a dedicated firmware. It is a general purpose DMA controller supporting 16 independent channels and data can be moved from memory to memory or between memory and paced latency critical real time targets. After quite

Hi Vinod, Bjorn, Patrice, This patchset adds support for the Flexible Direct Memory Access (FDMA) core found on STi chipsets from STMicroelectronics. The FDMA is a slim core CPU with a dedicated firmware. It is a general purpose DMA controller supporting 16 independent channels and data can be moved from memory to memory or between memory and paced latency critical real time targets. After quite

...:03 fwe0: Ethernet address: 06:e4:0a:4f:10:03 fwip0: <IP over FireWire> on firewire0 fwip0: Firewire address: 06:e4:0a:00:69:4f:10:03 @ 0xfffe00000000, S400, maxrec 2048 sbp0: <SBP-2/SCSI over FireWire> on firewire0 dcons_crom0: <dcons configuration ROM> on firewire0 dcons_crom0: bus_addr 0x138c000 fwohci0: Initiate bus reset fwohci0: BUS reset fwohci0: node_id=0xc800ffc0, gen=1, CYCLEMASTER mode isab0: <PCI-ISA bridge> at device 31.0 on pci0 isa0: <ISA bus> on isab0 atapci0: <Intel ICH4 UDMA100 controller> port 0x1f0-0x1f7,0x3f6,0x170-0x177,0x376,0x1860-0x186f at...

Hi, Is the http://xenbits.xensource.com/linux-2.6-xen.hg tree still being updated? if not, what''s the preferred Linux tree to track that has all of the Xen bits? Thanks, Muli _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

Hi all, Here''s a work in progress series whcih does a partial revert of the previous swiotlb changes, and does a partial replacement with Becky Bruce''s series. The most important difference is Becky''s use of phys_addr_t rather than page+offset to represent arbitrary pages. This turns out to be simpler. I didn''t replicate the map_single_page changes, since

Hi, This is third approach (complete this time) for replacing struct dma_attrs with unsigned long. The main patch (2/45) doing the change is split into many subpatches for easier review (3-43). They should be squashed together when applying. *Important:* Patchset is *only* build tested on allyesconfigs: ARM, ARM64, i386, x86_64 and powerpc. Please provide reviewes and tests for other

...0 (ROM=1) fwohci0: No. of Isochronous channels is 4. fwohci0: EUI64 00:11:d8:00:00:72:dc:3e fwohci0: Phy 1394a available S400, 2 ports. fwohci0: Link S400, max_rec 2048 bytes. firewire0: <IEEE1394(FireWire) bus> on fwohci0 dcons_crom0: <dcons configuration ROM> on firewire0 dcons_crom0: bus_addr 0x3e108000 fwe0: <Ethernet over FireWire> on firewire0 if_fwe0: Fake Ethernet address: 02:11:d8:72:dc:3e fwe0: Ethernet address: 02:11:d8:72:dc:3e fwip0: <IP over FireWire> on firewire0 fwip0: Firewire address: 00:11:d8:00:00:72:dc:3e @ 0xfffe00000000, S400, maxrec 2048 sbp0: <SBP-2/...