search for: br_cc

...CPU natively supports a conditional branch instruction that accepts a condition to test (equal, less than, etc.), two operands (two registers, or one register and one immediate), and finally a target PC to branch to if the comparison succeeds. Great -- that all seems to mesh directly with the ISD::BR_CC opcode. However... I can't seem to use 'brcc' or 'br_cc' in the .td file.  Neither is recognized as a valid keyword.  I can use 'brcond', but given the capabilities of the CPU I'm targeting, it seems better to implement BR_CC directly and do setOperationAction(ISD::...

Hello, I'd like to write some unit tests which verifies SELECT_CC and BR_CC lowering for ARM target, but I'm almost completely unfamiliar with llvm/Target. How can I get this nodes in DAG? Thanks. -- Kind regards, Dmitry Borisenkov -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachm...

...is method assumes that one will be able to get the predicate from the conditional branch instruction on which the conditional instruction depends. - So implicitly, this method assumes that the conditional branch instruction is a brcond-like instruction (which has a predicate operand), not a br_cc-like instruction (which does not have a predicate operand). - As far as I can see, no generic method is available to insert a predicate generating instruction that will replace the br_cc instruction. Is that correct? If so, what would be the best place in the code to implement and invoke f...

hi, i have a backend that want to do custom combine on SETCC nodes. but some time SETCC was combined into BR_CC before i can visit it to do my own combine, because DAGCombiner always do its own combine before custom combine. so, is there anyway to prevent it being combined without changing the logic of DAGCombiner? thank you very much --ether

hi Eli, thanks for reply :) i am currently decompose the BR_CC node to a target SETCC node and a target BRCOND node, but since BR_CC node sometimes is combine from a BRCOND node and SETCC node, so i just wondering if theres any better way :) regards --ether

On Fri, Dec 11, 2009 at 1:49 AM, ether zhhb <etherzhhb at gmail.com> wrote: > hi, > > i have a backend that want to do custom combine on SETCC nodes. > > but some time SETCC was combined into BR_CC before i can visit it to > do my own combine, because DAGCombiner always do its own combine > before custom combine. so, is there anyway to prevent it being > combined without changing the logic of DAGCombiner? If BR_CC isn't legal on your target, you shouldn't end up with any in...

Hello, Im back trying to finish my backend to a simple RISC cpu SABRE now that most of the tedious process of examining undergraduate students is out of the way. I have managed to describe the registers and the instructions in the architecture and have added support for 32 bit immediates (thanks to Christopher Lamb) as the instruction set only supports 17 bit immediates directly. Could

...list > llvm-dev at lists.llvm.org > http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev > I'd like to ask you another question (if you don't mind). My EsenciaISelLowering.cpp contains the following code in the EsenciaTargetLowering class constructor: setOperationAction(ISD::BR_CC, MVT::i32, Custom); setOperationAction(ISD::BR_CC, MVT::f32, Custom); setOperationAction(ISD::BR_JT, MVT::Other, Expand); setOperationAction(ISD::BRCOND, MVT::Other, Expand); setOperationAction(ISD::SETCC, MVT::i32, Expand); setOp...

Hi, I'm working on project which involves writing a backend for a hypothetical architecture. I am currently trying to figure out the best way to translate for loops to use a specialized "loop" instruction the architecture supports. The instruction is similar X86's loop instruction, where a register is automatically decremented and the condition is automatically checked to see if

...hs = DAG.getNode(ISD::ADD, MVT::i32, Callee, DAG.getConstant(4, MVT::i32)); Ops.push_back(Chain); Ops.push_back(DAG.getCondCode(ISD::SETEQ)); Ops.push_back(lhs); Ops.push_back(rhs); MachineBasicBlock *error_block; Ops.push_back(DAG.getBasicBlock(error_block)); Chain = DAG.getNode(ISD::BR_CC, MVT::Other, &Ops[0], Ops.size()); Now, there are, I guess, basically two things here: 3) How to access the value at address [callee + 4]? I guess, Callee won't work as a parameter for add, and the result of the add in the cmp instruction wont be interpreted as a memory location (but as a...

On Jul 1, 2009, at 2:22 PMPDT, Dan Gohman wrote: >> Ops.push_back(DAG.getConstant(1, MVT::i32)); >> Chain = DAG.getNode(ISD::ADD, DAG.getVTList(MVT::Other, MVT::i32), >> &Ops[0], Ops.size()); >> >> Isn't that the way how it is supposed to work? > > ADD does not use a chain, so there's no chain operand, or > MVT::Other result for it in an ADD

...gt; ordered grater than, if any input NaN then return false fcmp.ne --> ordered not equal, if any input NaN then return true fcmp.ge --> ordered grater equal, if any input NaN then return false When FPU is not present I need to generate a library call, so I have added following code in LowerBR_CC function in XXXISelLowering.cpp const XXXSubtarget &STI = static_cast<const XXXSubtarget&> (DAG.getSubtarget()); XXXCC::CondCodes TCC; getFPCCtoXXCC(CC,TCC); TargetCC = DAG.getConstant(TCC, dl, MVT::i8); if (STI.useHardFloat()) { /...

...e following code (as part of a larger function): %0 = icmp eq i16 %a, 0 ; <i1> [#uses=1] br i1 %0, label %bb1, label %bb I would like to match this with a BRCOND, but all I get is an error message when compiling the above code that say: LLVM ERROR: Cannot yet select: 0x170f200: ch = br_cc 0x170f000, 0x170ed00, 0x170dc60, 0x170ec00, 0x170ef00 [ID=19] 0x170f000: ch = TokenFactor 0x170e560, 0x170e760, 0x170e960 [ID=18] 0x170e560: ch = CopyToReg 0x16d5748, 0x170e460, 0x170df60 [ID=15] 0x16d5748: ch = EntryToken [ORD=1] [ID=0] 0x170e460: i16 = Register %reg16384 [ID=5]...

...any input NaN then return false > fcmp.ne --> ordered not equal, if any input NaN then return true > fcmp.ge --> ordered grater equal, if any input NaN then return false > > When FPU is not present I need to generate a library call, > > so I have added following code in LowerBR_CC function in > XXXISelLowering.cpp > > const XXXSubtarget &STI = static_cast<const XXXSubtarget&> > (DAG.getSubtarget()); > XXXCC::CondCodes TCC; > getFPCCtoXXCC(CC,TCC); > TargetCC = DAG.getConstant(TCC, dl, MVT::i8)...

I have hit a extreme case during a bootstrap. The DAG combiner canonicalizes <= 65536 into < 65537 The problem is that 65536 can de represented inline in a ARM instruction and 65537 cannot. I am considering changing the code that creates ARMCMP when lowering br_cc and set_cc nodes. Does anyone has a better solution? Best Regards, Rafael

Howdy, <---stuff deleted -----> Basically the architecture I want to compile to (SABRE) RISC does not support a conditional branch or a select instruction. It supports explicit branches of the form. blt %a, %b, imm // branch on less than iff %a < %b then pc = pc + imm So there are various branch instructions like .... ble, beq, bne, blt, bltu and bleu (unsigned) Im just

...ops. Can you please explain what is happening? It sounds like a bug we should fix. > > What is ideal place where I can convert unordered comparison to un > comparison + OR + ordered comparison ? > Can I do it by adding required SDNodes ? > for example I am trying to do it in LowerBR_CC as shown below: > getFPCCtoMBCC(CC,TCC); > TargetCC = DAG.getConstant(TCC, dl, MVT::i8); > Flag = DAG.getNode(XXXISD::FCMP, dl, MVT::Glue, LHS, RHS, > TargetCC); > if (isUnordered) { > TCC = XXX::COND_UN; > TargetCC =...

...nk, that at this point I need to stop LLVM from attempting to reuse the result of the CMP instruction before and after the function call, and instead make it generate a new cmp instruction after the call. But how do I achieve that? (maybe a difficulty is that I am Custom lowering ’’SELECT_CC’ and ‘BR_CC’, and Expanding ’SELECT’ and ‘BRCOND’, instead of the opposite? Does this make a difference?) Thanks Joan Lluch Tel: 620 28 45 13 > On 2 Jun 2019, at 03:23, Eli Friedman <efriedma at quicinc.com> wrote: > > There are basically two possible approaches here. > > One approac...

...atus Register already had the correct status flags. The cmp instruction in my architecture is the typical one that compares two registers, or a register with an immediate, and sets the Status Flags accordingly. I implemented my ‘cmp’ instruction in LLVM by custom lowering the SETCC, SELECT_CC and BR_CC in the usual way, mostly following the ARM implementation. In particular the target cmp instruction is created and glued to a target conditional instruction, such as a conditional branch, or a conditional select. The generated code may look like this: add R0, R1, R2 cmp R0, #0 breq Label This w...

You can tell LLVM that you have "sign extended" setCC results (all ones). Dan On Nov 18, 2008, at 5:33 PM, Eli Friedman wrote: > On Tue, Nov 18, 2008 at 1:56 PM, Villmow, Micah > <Micah.Villmow at amd.com> wrote: >> The IR produces correct results, but my backend does not and the >> only thing >> I can think of is that the IR is treating the