Displaying 20 results from an estimated 171 matches for "bne".
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2018 Jan 10
3
llvm-mc assembler, GNU as, and pc-relative branches for Arm/AArch64/Mips
...uld be great.
Please note: it's possible some of the differences I'm seeing are due to
different default ASM variants or default target options across tools
- do let me know
if it seems that's the case.
# Comparing Mips behaviour
$ cat test-mips.s
lab:
beq $6, $7, 128
bne $4, $5, 64
beq $6, $7, 128
bne $4, $5, 64
Assemble with llvm-mc: `llvm-mc -triple=mipsel-unknown-linux test-mips.s
-filetype=obj > foo.o` and then disassemble with `llvm-objdump -d -r`:
foo.o: file format ELF32-mips
Disassembly of section .text:
lab:
0: 20 00 c...
2023 Aug 18
1
Host key verification (known_hosts) with ProxyJump/ProxyCommand
...n, sslip.io
> might be helpful.
>
> https://sslip.io/
That's a handy little service? not sure of its long-term stability
though for production use, but one to have a closer look at and keep in
the memory bank.
It's not so much the DNS admin frowning on its use. I think the subnets
involved are /24s and our public DNS infrastructure is Amazon AWS
managed via Terraform, so it could be scripted if we wanted such detail
to be publicly visible. (And we do have a couple of private IPs visible
on our domain -- mostly so Let's Encrypt can validate the host exists.)
The b...
2023 Aug 18
2
Host key verification (known_hosts) with ProxyJump/ProxyCommand
On 18.08.23 07:39, Darren Tucker wrote:
> On Fri, 18 Aug 2023 at 15:25, Stuart Longland VK4MSL <me at vk4msl.com> wrote:
> [...]
>> The crux of this is that we cannot assume the local IPv4 address is
>> unique, since it's not (and in many cases, not even static).
>
> If the IP address is not significant, you can tell ssh to not record
> them ("CheckHostIP
2007 Mar 19
2
Warcraft 2 BNE - performance problem...
Hello to all.
I have recently installed my Warcraft 2 BNE under wine (Ubuntu 6.10 -
wine version 0.9.29). It runs almost perfect. There is intro, sounds
but... game itself is slow. I mean my machine (Duron 1200; 384 MB;
GeForce 5200 128 MB (drivers installed 9746); should run this game
flawless (and it does under Window$) - but unfortunately, under wine
g...
2018 Dec 04
2
Incorrect placement of an instruction after PostRAScheduler pass
...I’m facing a crash issue (--target=arm-linux-gnueabi
-march=armv8-a+crc -mfloat-abi=hard) and debugging the problem, I
found that an intended branch was not taken due to bad code generation
after the Post RA Scheduler pass. A CMPri instruction after an
INLINEASM block (which inturn contains a cmp, bne instruction) is
being moved before the INLINEASM block incorrectly resulting in two
consecutive bne instructions.
I do not have a small convenient test case and there are several
inline functions involved, but I hope to explain the problem with
relevant code snippets. Any suggestions on what/where...
2012 Jan 12
1
[LLVMdev] A question of Sparc assembly generated by llc
...tr), %l1
or %g0, %l1, %o0
call printf
nop
ld [%fp+-12], %o2
ld [%fp+-8], %l2
sethi %hi(.L.strQ521), %l3
add %l3, %lo(.L.strQ521), %o0
or %g0, %l2, %o1
call MY_FUNCTION
nop
or %g0, 1, %i0
(subcc %l1, 0, %l1 ! This line is added by me. It was not there)
bne .LBB0_2
nop
! BB#1:
subcc %l2, 0, %l2
or %g0, %l0, %i0
.LBB0_2:
.......
I am not an expert on Sparc assembly, but I read from somewhere that
branching instructions are set by the statues flags. The first 'bne'
statement appeared before any subcc or any other cc opcodes. T...
2020 Jul 06
0
[PATCH v3 3/6] powerpc: move spinlock implementation to simple_spinlock
...he lock, so we succeeded
+ * in getting the lock if the return value is 0.
+ */
+static inline unsigned long __arch_spin_trylock(arch_spinlock_t *lock)
+{
+ unsigned long tmp, token;
+
+ token = LOCK_TOKEN;
+ __asm__ __volatile__(
+"1: " PPC_LWARX(%0,0,%2,1) "\n\
+ cmpwi 0,%0,0\n\
+ bne- 2f\n\
+ stwcx. %1,0,%2\n\
+ bne- 1b\n"
+ PPC_ACQUIRE_BARRIER
+"2:"
+ : "=&r" (tmp)
+ : "r" (token), "r" (&lock->slock)
+ : "cr0", "memory");
+
+ return tmp;
+}
+
+static inline int arch_spin_trylock(arch_spinlock_t *loc...
2016 Sep 07
2
[PowerPC] Recent branch too far breakage
...m getting an assembler error when building
PPCInstPrinter.cpp:
The error is:
/tmp/PPCInstPrinter-84c835.s: Assembler messages:
/tmp/PPCInstPrinter-84c835.s:7671: Error: operand out of range
(0x0000000000008004 is not between 0xffffffffffff8000 and
0x0000000000007ffc)
The offending line is the bne branch in this snippet:
.LBB24_787:
ld 3, 16(29)
ld 4, 24(29)
sub 4, 4, 3
rldicl 4, 4, 60, 4
cmplwi 0, 4, 3
bne 0, .LBB24_2630
Could this be because of a recent change in the PowerPC code generator
or just because PPCInstPrinter.cpp...
2016 Sep 07
2
[PowerPC] Recent branch too far breakage
...error is:
> >
> > /tmp/PPCInstPrinter-84c835.s: Assembler messages:
> > /tmp/PPCInstPrinter-84c835.s:7671: Error: operand out of range
> > (0x0000000000008004 is not between 0xffffffffffff8000 and
> > 0x0000000000007ffc)
> >
> > The offending line is the bne branch in this snippet:
> >
> > .LBB24_787:
> > ld 3, 16(29)
> > ld 4, 24(29)
> > sub 4, 4, 3
> > rldicl 4, 4, 60, 4
> > cmplwi 0, 4, 3
> > bne 0, .LBB24_2630
> >
> > Could...
2007 Jul 12
1
[LLVMdev] backend problem with LiveInterval::removeRange
...8>
0x88c95a8: ch = brcond 0x88c8fc8:1, 0x88c88f8, 0x88c9540
entry: 0x88c7918, LLVM BB @0x88bf1f8, ID#0:
Successors according to CFG: 0x88c7db8 (#2) 0x88c79a8 (#1)
===== Instruction selection begins:
Selecting: 0x88c95a8: ch = brcond 0x88c8fc8:1, 0x88c88f8, 0x88c9540
=> 0x88c8970: ch = BNE 0x88c8fc8, 0x88c9060, 0x88c9540, 0x88c8fc8:1
Selecting: 0x88c9540: ch = BasicBlock <cond_false 0x88c7db8>
=> 0x88c9540: ch = BasicBlock <cond_false 0x88c7db8>
Selecting: 0x88c9060: i32 = Constant <2>
=> 0x88c9060: i32 = ADDiu 0x88c9360, 0x88c88f8
Selecting: 0x88c8fc8: i32,ch...
1999 Jul 06
0
Force Group and NFS mounted dir problems
...king the "force
group" config option work as expected. To make matters more interesting the
file system being samba-shared is mounted from another unix server.
To explain:
Machine "marvin" (Solaris 2.7) exports /mnt/anthias using (/etc/dfs/dfstab):
share -F nfs -o root=forty2.bne.marine.csiro.au:reef2.bne.marine.csiro.au,
rw=forty2.bne.marine.csiro.au:reef2.bne.marine.csiro.au /mnt/anthias
Machine forty2 (Solaris 2.5.1) mounts this as /mnt/anthias. Forty2 runs the
samba server.
I have defined the share as
[anthias]
path = /mnt/anthias
writable = yes...
2013 May 21
0
[PATCH] 02-
...te last x sample to q5 for next "previous" sample vector
+ * I know this last sentence is tricky :) */
+ "vdup.s16 q5, d3[3];\n"
+
+ /* Store 16 y results */
+ "vst1.16 {q2-q3}, [%2]!;\n"
+
+ "subs %5, %5, #1;\n"
+ "bne .celt_fir1_process16_%=;\n"
+ ".celt_fir1_process16_done_%=:\n"
+
+ /* Check if some samples remains */
+ "ands %5, %3, #15;\n"
+ "beq .celt_fir1_done_%=;\n"
+
+ /* Process remaining samples one by one with NEON
+ * Previous sample...
2011 Sep 01
0
[PATCH 5/5] resample: Add NEON optimized inner_product_single for floating point
...DE_INNER_PRODUCT_SINGLE
+/* Only works when len % 4 == 0 */
+static inline float inner_product_single(const float *a, const float *b, unsigned int len)
+{
+ float ret;
+ uint32_t remainder = len % 16;
+ len = len - remainder;
+
+ asm volatile (" cmp %[len], #0\n"
+ " bne 1f\n"
+ " vld1.32 {q4}, [%[b]]!\n"
+ " vld1.32 {q8}, [%[a]]!\n"
+ " subs %[remainder], %[remainder], #4\n"
+ " vmul.f32 q0, q4, q8\n"
+ " bne 4f\n"
+ " b 5f\n"
+ "1:"
+ " vld1.32 {q4,...
2013 May 21
2
[PATCH] 02-Add CELT filter optimizations
...te last x sample to q5 for next "previous" sample vector
+ * I know this last sentence is tricky :) */
+ "vdup.s16 q5, d3[3];\n"
+
+ /* Store 16 y results */
+ "vst1.16 {q2-q3}, [%2]!;\n"
+
+ "subs %5, %5, #1;\n"
+ "bne .celt_fir1_process16_%=;\n"
+ ".celt_fir1_process16_done_%=:\n"
+
+ /* Check if some samples remains */
+ "ands %5, %3, #15;\n"
+ "beq .celt_fir1_done_%=;\n"
+
+ /* Process remaining samples one by one with NEON
+ * Previous sample...
2007 Dec 02
2
Optimised qmf_synth and iir_mem16
...]
mla r10, r0, r14,r11 @ mem[5] = mem[6] - den[5]*y[i]
ldrsh r0, [r1, #14]
mla r11, r4, r14,r12 @ mem[6] = mem[7] - den[6]*y[i]
subs r3, r3, #1
mul r12, r0, r14 @ mem[7] = -den[7]*y[i]
ldr r0, [sp], #4 @ restore r0
bne 0b
ldr r4, [sp, #40] @ r4 = mem
stmia r4, { r5-r12 } @ Save back mem[]
ldmia sp!, { r4-r11, pc } @ Exit
.order_10:
ldmia r4, { r5-r9 } @ r5-r9 = mem[0..4]
add r5, r5, #4096 @ Rounding constant
ldrsh r14, [r0], #...
2018 Apr 27
2
[DbgInfo] Potential bug in location list address ranges
...34: poplt {r4, r6, r7, pc} // a
function return
8136: ldrb.w ip, [r1, #3]
813a: ldrb.w lr, [r4, #3]
813e: movs r0, #85 ; 0x55
8140: cmp lr, ip
8142: bne.n 8168 <foo+0x44>
8144: ldrb.w ip, [r1, #2]
8148: ldrb r3, [r4, #2]
814a: cmp r3, ip
814c: it ne
814e: popne {r4, r6, r7, pc} // a function
return
8150...
2020 Jul 03
7
[PATCH v2 0/6] powerpc: queued spinlocks and rwlocks
v2 is updated to account for feedback from Will, Peter, and
Waiman (thank you), and trims off a couple of RFC and unrelated
patches.
Thanks,
Nick
Nicholas Piggin (6):
powerpc/powernv: must include hvcall.h to get PAPR defines
powerpc/pseries: move some PAPR paravirt functions to their own file
powerpc: move spinlock implementation to simple_spinlock
powerpc/64s: implement queued
2020 Jul 21
2
[PATCH v3 0/6] powerpc: queued spinlocks and rwlocks
...val;
+
+again:
+ asm volatile(
+"1:\t" PPC_LWARX(%0,0,%1,1) " # queued_spin_lock \n"
+ : "=&r" (val)
+ : "r" (&a->counter)
+ : "memory");
+
+ if (likely(val == 0)) {
+ asm_volatile_goto(
+ " stwcx. %0,0,%1 \n"
+ " bne- %l[again] \n"
+ "\t" PPC_ACQUIRE_BARRIER " \n"
+ :
+ : "r"(_Q_LOCKED_VAL), "r" (&a->counter)
+ : "cr0", "memory"
+ : again );
return;
-
- queued_spin_lock_slowpath(lock, val);
+ }
+
+ if (likely(val == _Q_LOCK...
2020 Jul 21
2
[PATCH v3 0/6] powerpc: queued spinlocks and rwlocks
...val;
+
+again:
+ asm volatile(
+"1:\t" PPC_LWARX(%0,0,%1,1) " # queued_spin_lock \n"
+ : "=&r" (val)
+ : "r" (&a->counter)
+ : "memory");
+
+ if (likely(val == 0)) {
+ asm_volatile_goto(
+ " stwcx. %0,0,%1 \n"
+ " bne- %l[again] \n"
+ "\t" PPC_ACQUIRE_BARRIER " \n"
+ :
+ : "r"(_Q_LOCKED_VAL), "r" (&a->counter)
+ : "cr0", "memory"
+ : again );
return;
-
- queued_spin_lock_slowpath(lock, val);
+ }
+
+ if (likely(val == _Q_LOCK...
2011 Sep 01
6
[PATCH 0/5] ARM NEON optimization for samplerate converter
From: Jyri Sarha <jsarha at ti.com>
I optimized Speex resampler for NEON capable ARM CPUs. The first patch
should speed up resampling on any platform that can spare the
increased memory usage. It would be nice to have these merged to the
master branch. Please let me know if there is anything I can do to
help the the merge. The patches have been rebased on top of master
branch in