search for: bjorne

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2005 Jun 17
5
Presence and IM?
We have been running Asterisk for about a month now and one of the things I miss the most is the ability to se who's online and available and who's not. Surely, there's the manager interface, but unless you'd want to install extra software on each client computer, this is not a good option. Then there's the presence / IM function in SIP. Since we're only using SIP
2018 Mar 11
3
[PATCH v2 0/7] Modernize vga_switcheroo by using device link for HDA
On Tue, Mar 06, 2018 at 11:29:40AM +0100, Daniel Vetter wrote: > On Sat, Mar 03, 2018 at 10:53:24AM +0100, Lukas Wunner wrote: > > Modernize vga_switcheroo by using a device link to enforce a runtime PM > > dependency from an HDA controller to the GPU it's integrated into, v2. > > > > https://github.com/l1k/linux/commits/switcheroo_devlink_v2 > > This all
2012 Nov 01
0
[LLVMdev] : Predication on SIMD architectures and LLVM
On Wed, Oct 31, 2012 at 09:13:43PM +0100, Bjorn De Sutter wrote: > Hi all, > > I am working on a CGRA backend (something like a 2D VLIW), and we also absolutely need predication. I extended the IfConversion pass to allow it to be executed multiple times and to predicate already predicated code. This is necessary to predicate code with nested conditional statements. At this point, we
2012 Oct 31
3
[LLVMdev] : Predication on SIMD architectures and LLVM
Hi all, I am working on a CGRA backend (something like a 2D VLIW), and we also absolutely need predication. I extended the IfConversion pass to allow it to be executed multiple times and to predicate already predicated code. This is necessary to predicate code with nested conditional statements. At this point, we support or, and, and conditional predicates (see Scott Mahlke's papers on this
2012 Mar 06
2
[LLVMdev] Recent changes to MCRegisterClass fields: uint8_t is too narrow
Hi all, in r152019 (from ctopper), the number of available registers of any type in a machine description is decreased to 256 because it needs to be encoded in uint8_t now. I'm trying to support an experimental embedded architecture with more registers (out of tree), but now that becomes impossible. Anyone knows a solution? Thanks, Bjorn De Sutter Computer Systems Lab Ghent University
2018 Apr 19
4
[PATCH] virtio_ring: switch to dma_XX barriers for rpmsg
virtio is using barriers to order memory accesses, thus dma_wmb/rmb is a good match. Build-tested on x86: Before [mst at tuck linux]$ size drivers/virtio/virtio_ring.o text data bss dec hex filename 11392 820 0 12212 2fb4 drivers/virtio/virtio_ring.o After mst at tuck linux]$ size drivers/virtio/virtio_ring.o text data bss dec hex filename
2018 Apr 19
4
[PATCH] virtio_ring: switch to dma_XX barriers for rpmsg
virtio is using barriers to order memory accesses, thus dma_wmb/rmb is a good match. Build-tested on x86: Before [mst at tuck linux]$ size drivers/virtio/virtio_ring.o text data bss dec hex filename 11392 820 0 12212 2fb4 drivers/virtio/virtio_ring.o After mst at tuck linux]$ size drivers/virtio/virtio_ring.o text data bss dec hex filename
2020 Jul 01
3
[PATCH 2/2] virtio-mmio: Reject invalid IRQ 0 command line argument
From: Bjorn Helgaas <bhelgaas at google.com> The "virtio_mmio.device=" command line argument allows a user to specify the size, address, and IRQ of a virtio device. Previously the only requirement for the IRQ was that it be an unsigned integer. Zero is an unsigned integer but an invalid IRQ number, and after a85a6c86c25be ("driver core: platform: Clarify that IRQ 0 is
2020 Jul 01
3
[PATCH 2/2] virtio-mmio: Reject invalid IRQ 0 command line argument
From: Bjorn Helgaas <bhelgaas at google.com> The "virtio_mmio.device=" command line argument allows a user to specify the size, address, and IRQ of a virtio device. Previously the only requirement for the IRQ was that it be an unsigned integer. Zero is an unsigned integer but an invalid IRQ number, and after a85a6c86c25be ("driver core: platform: Clarify that IRQ 0 is
2012 Mar 06
0
[LLVMdev] Recent changes to MCRegisterClass fields: uint8_t is too narrow
I changed it to uint16_t in r152100. Is that enough for your architecture? On Tue, Mar 6, 2012 at 12:24 AM, Bjorn De Sutter < bjorn.desutter at elis.ugent.be> wrote: > Hi all, > > in r152019 (from ctopper), the number of available registers of any type > in a machine description is decreased to 256 because it needs to be encoded > in uint8_t now. I'm trying to support an
2012 Nov 27
2
[LLVMdev] strange dbgs() behavior: unable to print floats in machine backend
Hi, that solved my problem on trunk as well, thanks. Strange that you have to include this though. Bjorn On 27 Nov 2012, at 00:00, Daniel Prokesch <daniel.prokesch at gmail.com> wrote: > Hi, > > I accidentally stumbled upon your post. > I observed similar behaviour whenever I did not include > > #include "llvm/Support/Debug.h" > #include
2011 Nov 14
2
[LLVMdev] alias analysis in ScheduleDagInstr class
Hi Sergei, thanks for considering my question. We if-convert some code, such that the basic block looks as follows after if-conversion: ld char from A into R1 p1 = R1>255? (generate the predicate) p1 | R1 = 255 (conditional execution) st char R1 to A ld char from A+1 into R2 p2 = R2>255? (generate the predicate) p2 | R2 = 255 (conditional execution) store char R2 to A+1 The problem is
2011 Nov 14
0
[LLVMdev] alias analysis in ScheduleDagInstr class
We observed exact same problem, and I did put in place a mechanism to recognize and break such false dependencies right before pre-RA scheduler (in DAG->DAG lowering), but the immediate observed effect for our back end was performance reduction, since none of the current schedulers were capable of dealing with newly presented parallelism in BB (resulted in high reg pressure and
2012 Nov 27
1
[LLVMdev] strange dbgs() behavior: unable to print floats in machine backend
Hi Craig, I updated from the trunk some minutes ago, and thus got the "explicit". PrintReg constructor. When I do not include raw_ostream.h after including Debug.h in the backend cpp files, I now get compilation errors, not only when trying to print floats but also in other places. For example, for the code bool ADRESRegisterInfo::hasReservedCallFrame(const MachineFunction &MF)
2012 Nov 27
0
[LLVMdev] strange dbgs() behavior: unable to print floats in machine backend
Can you try making the constructor "explicit" for PrintReg in include/llvm/Target/TargetRegisterInfo.h. I think you were getting an implicit conversion there which should probably be fixed anyway. On Mon, Nov 26, 2012 at 11:47 PM, Bjorn De Sutter < bjorn.desutter at elis.ugent.be> wrote: > Hi, > > that solved my problem on trunk as well, thanks. Strange that you have to
2006 Oct 24
2
Unable to load foreign after upgrade on ubuntu
I am running R on ubuntu dapper. The version that is in the ubuntu repos is 2.2.1, so I decided to upgrade by adding deb http://cran.R-project.org/bin/linux/ubuntu dapper/ to my sources.list, as advised on the web page. After sudo apt-get update and upgrade, I have version 2.3.1. However, when I try to load the library 'foreign', I get the following error: Error in dyn.load(x,
2019 Apr 04
4
[PATCH] pci/quirks: Add quirk to reset nvgpu at boot for the Lenovo ThinkPad P50
[+cc Hans, author of 0b2fe6594fa2 ("drm/nouveau: Queue hpd_work on (runtime) resume")] On Fri, Mar 22, 2019 at 06:30:15AM -0500, Bjorn Helgaas wrote: > On Thu, Mar 21, 2019 at 05:48:19PM -0500, Bjorn Helgaas wrote: > > On Wed, Mar 13, 2019 at 06:25:02PM -0400, Lyude Paul wrote: > > > On Fri, 2019-02-15 at 16:17 -0500, Lyude Paul wrote: > > > > On Thu,
2013 Jan 21
2
[LLVMdev] introducing sign extending halfword loads into the LLVM IR
On 21 Jan 2013, at 14:39, Justin Holewinski <justin.holewinski at gmail.com> wrote: > Instruction selection happens on a different IR: SelectionDAG. In this IR, there are sign-extending loads that the IR converter will use, and are used for example to load 8/16-bit values into 32-bit registers (with sign or zero extension). Any optimizations performed during codegen will be in this
2013 Jan 21
3
[LLVMdev] introducing sign extending halfword loads into the LLVM IR
On Jan 21, 2013, at 6:34 AM, Justin Holewinski <justin.holewinski at gmail.com> wrote: > > On Mon, Jan 21, 2013 at 9:16 AM, Bjorn De Sutter <bjorn.desutter at elis.ugent.be> wrote: > On 21 Jan 2013, at 14:39, Justin Holewinski <justin.holewinski at gmail.com> wrote: > >> Instruction selection happens on a different IR: SelectionDAG. In this IR, there are
2013 Jan 21
0
[LLVMdev] introducing sign extending halfword loads into the LLVM IR
On Mon, Jan 21, 2013 at 9:16 AM, Bjorn De Sutter < bjorn.desutter at elis.ugent.be> wrote: > On 21 Jan 2013, at 14:39, Justin Holewinski <justin.holewinski at gmail.com> > wrote: > > Instruction selection happens on a different IR: SelectionDAG. In this > IR, there are sign-extending loads that the IR converter will use, and are > used for example to load 8/16-bit