Displaying 11 results from an estimated 11 matches for "bitop1".
Did you mean:
bitops
2016 Aug 22
3
Instruction itineraries and fence/barrier instructions
...load volatile i32* @read_me, align 4
ret i32 %1
}
Prior to adding our instruction itineraries the code generated was:
xstg_intrinsic: # @xstg_intrinsic
# BB#0: # %entry
subI r509, r509, 16, 64
store r510, r509, 0, 64
bitop1 r510, r509, 0, OR, 64
store r0, r510, 12, 32
movimm r1, %hi(write_me), 64
movimmshf32 r1, r1, %lo(write_me)
store r0, r1, 0, 32
fence 2
movimm r0, %hi(read_me), 64
movimmshf32 r0, r0, %lo(read_me)
load r1, r0, 0, 32...
2016 Aug 22
2
Instruction itineraries and fence/barrier instructions
...to adding our instruction itineraries the code generated was:
> >
> > xstg_intrinsic: # @xstg_intrinsic
> > # BB#0: # %entry
> > subI r509, r509, 16, 64
> > store r510, r509, 0, 64
> > bitop1 r510, r509, 0, OR, 64
> > store r0, r510, 12, 32
> > movimm r1, %hi(write_me), 64
> > movimmshf32 r1, r1, %lo(write_me)
> > store r0, r1, 0, 32
> > fence 2
> > movimm r0, %hi(read_me), 64
> >...
2016 Jan 07
2
TableGen error message: top-level forms in instruction pattern should have void types
...ign 4
store i8** %argv, i8*** %argv.addr, align 8
%0 = load i32 addrspace(4)* @answer, align 4
store i32 %0, i32* @xint, align 4
...
Currently this produces the following assembly code:
.Ltmp0:
.cfi_def_cfa_offset 48
store r510, r509, 0, 64
.Ltmp1:
.cfi_offset 510, -48
bitop1 r510, r509, 0, OR, 64
.Ltmp2:
.cfi_def_cfa_register 510
store r0, r510, 44, 32
store r1, r510, 32, 64
movimm r0, %hi(xint), 64
movimmshf32 r0, r0, %lo(xint)
movimm r1, %rel(answer), 64 #<--- relevant lines
load r1, r1, 0,...
2016 Nov 03
2
rotl: undocumented LLVM instruction?
...r1, r1, -1, 64
bclr r1, r0, r1, 64
jabs r511
Whereas with 3.9 the generated code is:
bclr64: # @bclr64
# BB#0: # %entry
addI r1, r1, -1, 64
movimm r2, -2, 64
rol r1, r2, r1, 64
bitop1 r1, r0, r1, AND, 64
jabs r511
... it seems to be negatively impacting some of our larger benchmarks as
well that used to contains several bclr (bit clear) commands but now
contain much less.
Phil
On Wed, Nov 2, 2016 at 4:10 PM, Ryan Taylor <ryta1203 at gmail.com> wrot...
2016 Nov 03
3
rotl: undocumented LLVM instruction?
...gt;> Whereas with 3.9 the generated code is:
>>
>> bclr64: # @bclr64
>> # BB#0: # %entry
>> addI r1, r1, -1, 64
>> movimm r2, -2, 64
>> rol r1, r2, r1, 64
>> bitop1 r1, r0, r1, AND, 64
>> jabs r511
>>
>>
>> ... it seems to be negatively impacting some of our larger benchmarks as
>> well that used to contains several bclr (bit clear) commands but now
>> contain much less.
>>
>> Phil
>>
>...
2016 Dec 22
2
struct bitfield regression between 3.6 and 3.9 (using -O0)
...is is only an issue with -O0,
higher levels of optimization work fine)
After some investigation we discovered the problem, here's the relevant
part of our assembly generated by LVM 3.9:
load r0, r510, 24, 8
slr r0, r0, 1, 8
cmpimm r0, r0, 1, 0, 8, SNE
bitop1 r0, r0, 1<<0, AND, 64
jct .LBB0_2, r0, 0, N
jrel .LBB0_1
Notice the slr (shift logical right) instruction there is shifting to the
right 1 position in order to get flags.foo into bit 0 of r0. But the
problem is that the compare(cmpimm) is comparing not just...
2016 Dec 22
0
struct bitfield regression between 3.6 and 3.9 (using -O0)
...vels of optimization work fine)
>
> After some investigation we discovered the problem, here's the
> relevant part of our assembly generated by LVM 3.9:
>
> load r0, r510, 24, 8
> slr r0, r0, 1, 8
> cmpimm r0, r0, 1, 0, 8, SNE
> bitop1 r0, r0, 1<<0, AND, 64
> jct .LBB0_2, r0, 0, N
> jrel .LBB0_1
>
> Notice the slr (shift logical right) instruction there is shifting to
> the right 1 position in order to get flags.foo into bit 0 of r0. But
> the problem is that the compare(...
2016 Nov 03
2
rotl: undocumented LLVM instruction?
...is:
>
> bclr64: # @bclr64
> # BB#0: # %entry
> addI r1, r1, -1, 64
> movimm r2, -2, 64
> rol r1, r2, r1, 64
> bitop1 r1, r0, r1, AND, 64
> jabs r511
>
>
> ... it seems to be negatively impacting some of our larger
> benchmarks as well that used to contains several bclr (bit
> clear) commands but now contain much less.
>
>...
2016 Jan 07
2
TableGen error message: top-level forms in instruction pattern should have void types
On Thu, Jan 7, 2016 at 12:21 PM, Krzysztof Parzyszek via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> On 1/7/2016 1:55 PM, Phil Tomson via llvm-dev wrote:
>
>>
>> let Uses= [GRP] in {
>> def RelAddr : XSTGPseudo< (outs),
>> (ins GPRC:$spoff, GPRC:$dst),
>>
2016 Dec 23
2
struct bitfield regression between 3.6 and 3.9 (using -O0)
...evels of optimization work fine)
>
> After some investigation we discovered the problem, here's the relevant
> part of our assembly generated by LVM 3.9:
>
> load r0, r510, 24, 8
> slr r0, r0, 1, 8
> cmpimm r0, r0, 1, 0, 8, SNE
> bitop1 r0, r0, 1<<0, AND, 64
> jct .LBB0_2, r0, 0, N
> jrel .LBB0_1
>
> Notice the slr (shift logical right) instruction there is shifting to the
> right 1 position in order to get flags.foo into bit 0 of r0. But the
> problem is that the compare(c...
2016 Nov 02
3
rotl: undocumented LLVM instruction?
We've recently moved our project from LLVM 3.6 to LLVM 3.9. I noticed one
of our code generation tests is breaking in 3.9.
The test is:
; RUN: llc < %s -march=xstg | FileCheck %s
define i64 @bclr64(i64 %a, i64 %b) nounwind readnone {
entry:
; CHECK: bclr r1, r0, r1, 64
%sub = sub i64 %b, 1
%shl = shl i64 1, %sub
%xor = xor i64 %shl, -1
%and = and i64 %a, %xor
ret i64