search for: bit0

If HVM guest Fedora 7 uses PIT and lapic timer, it can''t boot or install. The cause is: At some point, Fedora 7 disables PIT interrupt by "vioapic.redirtbl[2].mask = 1, vpic.imr.bit0 = 0 (unmasked), vlapic.lvt[LINT0].mask = 1", and enables vlapic timer interrupt generating; In vmx_intr_assist() -> pt_update_irq(), we always choose IRQ0 rather than vlapic timer interrupt, because: 1) is_isa_irq_masked(v, 0) returns false due to vpic.imr.bit0 = 0; 2) the PIT''s p...

...(http://www.networkupstools.org/ups-protocols/powercom/Software_USB_comm unication_controller_BNT_series.doc), which overrides the semantics of the seconds field of USB HID Set Report command. As reported in document: Byte 13, Byte 14 (min, sec) If Byte(sec), bit7=0 and bit6=0 Then If Byte 9, bit0=1 Then command 185, 188, min, sec If Byte 9, bit0=0 Then command 186, 188, min, sec If Byte(sec), bit7=0 and bit6=1 Then command 185, 188, min, sec If Byte(sec), bit7=1 and bit6=0 Then command 186, 188, min, sec If Byte(sec), bit7=1 and bit6=1 Then no actions OR with 0x4000 sets the bit6 of se...

HI Folks, I've got two boxes that I recently moved from -stable to 9.1rc1. I did them one at a time, with about a week between the upgrades. After the first upgrade, I noticed something strange with networking but didn't really dig into it much. After the second upgrade immediately experiencing the same issues, I figured it seemed to be something related to 9.1rc1. What I am finding

...st be + * established. Otherwise, these requests in hw queue might never be + * dispatched. + * + * For example, there is a single hw queue (hctx) and two CPU queues (ctx0 + * for CPU0, and ctx1 for CPU1). + * + * Now CPU1 is just onlined and a request is inserted into ctx1->rq_list + * and set bit0 in pending bitmap as ctx1->index_hw is still zero. + * + * And then while running hw queue, blk_mq_flush_busy_ctxs() finds bit0 is set + * in pending bitmap and tries to retrieve requests in hctx->ctxs[0]->rq_list. + * But htx->ctxs[0] is a pointer to ctx0, so the request in ctx1->rq...

On 11/21/2017 07:39 PM, Jens Axboe wrote: > On 11/21/2017 11:27 AM, Jens Axboe wrote: >> On 11/21/2017 11:12 AM, Christian Borntraeger wrote: >>> >>> >>> On 11/21/2017 07:09 PM, Jens Axboe wrote: >>>> On 11/21/2017 10:27 AM, Jens Axboe wrote: >>>>> On 11/21/2017 03:14 AM, Christian Borntraeger wrote: >>>>>> Bisect

On 11/21/2017 07:39 PM, Jens Axboe wrote: > On 11/21/2017 11:27 AM, Jens Axboe wrote: >> On 11/21/2017 11:12 AM, Christian Borntraeger wrote: >>> >>> >>> On 11/21/2017 07:09 PM, Jens Axboe wrote: >>>> On 11/21/2017 10:27 AM, Jens Axboe wrote: >>>>> On 11/21/2017 03:14 AM, Christian Borntraeger wrote: >>>>>> Bisect

...these requests in hw queue might never be > + * dispatched. > + * > + * For example, there is a single hw queue (hctx) and two CPU queues (ctx0 > + * for CPU0, and ctx1 for CPU1). > + * > + * Now CPU1 is just onlined and a request is inserted into ctx1->rq_list > + * and set bit0 in pending bitmap as ctx1->index_hw is still zero. > + * > + * And then while running hw queue, blk_mq_flush_busy_ctxs() finds bit0 is set > + * in pending bitmap and tries to retrieve requests in hctx->ctxs[0]->rq_list. > + * But htx->ctxs[0] is a pointer to ctx0, so the re...

...these requests in hw queue might never be > + * dispatched. > + * > + * For example, there is a single hw queue (hctx) and two CPU queues (ctx0 > + * for CPU0, and ctx1 for CPU1). > + * > + * Now CPU1 is just onlined and a request is inserted into ctx1->rq_list > + * and set bit0 in pending bitmap as ctx1->index_hw is still zero. > + * > + * And then while running hw queue, blk_mq_flush_busy_ctxs() finds bit0 is set > + * in pending bitmap and tries to retrieve requests in hctx->ctxs[0]->rq_list. > + * But htx->ctxs[0] is a pointer to ctx0, so the re...

...on some firmware. Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=104791 Fixes: 5addcf0a5f0fad ("nouveau: add runtime PM support (v0.9)") Signed-off-by: Peter Wu <peter at lekensteyn.nl> --- Hi, I am not sure what exactly 0x1B is used for, it seems related to HDMI (Audio?). Bit0 of Arg3 is "OPFL", bit 1 is "OPVL" according to some firmware. On some laptops (P651RA) it sets "SGFL" (Switchable Graphics FLags?), on others it has no side-effects but returns a value based on Arg3 (Clevo P155M). A Medion P7624 stores values to "OPTF" (OPT...

Where can I find the Header file or whatever which specifies the "Mapping" flag. In feb - apr 2007, there was a lot of discussion about Ambisonics and Monty kindly stated that Mapping = 1 ; Denotes and Ambisonic file as opposed to = 0 which is 1 speaker/ 1 channel Has this been written explicitly into the standard? Which standard should I be looking at?

Hi everyone, today I got an e-mail from a company claiming that my server is doing port scans on their firewall machine. I found that hard to believe so I started checking the box. The company rep told me that the scan was originating at port 80 with destination port 8254 on their machine. I couldn't find any hints as to why that computer was subject to the alleged port scans. Searching

...]; + uint32_t second_chroma_qp_index_offset; // 1c8 + uint32_t u1cc; // 1cc + uint32_t curr_pic_order_cnt; // 1d0 + uint32_t field_order_cnt[2]; // 1d4 + uint32_t curr_mvidx; // 1dc + struct iref { + uint32_t u00; // 00 + uint32_t field_is_ref; // 04 // bit0: top, bit1: bottom + uint8_t is_long_term; // 08 + uint8_t non_existing; // 09 + uint32_t frame_idx; // 0c + uint32_t field_order_cnt[2]; // 10 + uint32_t mvidx; // 18 + uint8_t field_pic_flag; // 1c + // 20 + } refs[0x10]; // 1e0 + } i...

...]; + uint32_t second_chroma_qp_index_offset; // 1c8 + uint32_t u1cc; // 1cc + uint32_t curr_pic_order_cnt; // 1d0 + uint32_t field_order_cnt[2]; // 1d4 + uint32_t curr_mvidx; // 1dc + struct iref { + uint32_t u00; // 00 + uint32_t field_is_ref; // 04 // bit0: top, bit1: bottom + uint8_t is_long_term; // 08 + uint8_t non_existing; // 09 + uint32_t frame_idx; // 0c + uint32_t field_order_cnt[2]; // 10 + uint32_t mvidx; // 18 + uint8_t field_pic_flag; // 1c + // 20 + } refs[0x10]; // 1e0 + } i...