search for: binaryoper

I am trying to make some modifications to our code generator that will produce better code, but require adding new patterns. What I am trying to do is take a register/register pattern and change it to a register/immediate. So for example, I have this pattern: class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction { let Namespace =

I'm not at the machine that has the changes, but it was failing at index 0. Micah From: Owen Anderson [mailto:resistor at mac.com] Sent: Thursday, April 19, 2012 3:35 PM To: Villmow, Micah Cc: LLVM Developers Mailing List Subject: Re: [LLVMdev] Tablegen to match a literal in an instruction Micah, I don't see anything wrong with this offhand. Have you tried getting the debug output

Micah, I don't see anything wrong with this offhand. Have you tried getting the debug output from llc -debug, and matching it up with the state machine in your DAGISel.inc to see at what step the auto-generated matcher is failing to match your and-with-immediate? -Owen On Apr 19, 2012, at 3:07 PM, "Villmow, Micah" <Micah.Villmow at amd.com> wrote: > I am trying to make

Right, it's failing when it tries to materialize a move of a constant into a register. But it's only trying to do that because it previously failed to fold the constant into the AND. What you need to do is step through the path it takes when matching the AND node, and try to figure out why it ends up selecting the register-register version rather than the register-immediate version.

...place X * (2^C+/-1) with (X << C) -/+ X APInt Plus1 = *IVal + 1; APInt Minus1 = *IVal - 1; int isPow2 = Plus1.isPowerOf2() ? 1 : Minus1.isPowerOf2() ? -1 : 0; if (isPow2) { APInt &Pow2 = isPow2 > 0 ? Plus1 : Minus1; Value *Shl = Builder.CreateShl(Op0, Pow2.logBase2()); return BinaryOperator::Create(isPow2 > 0 ? BinaryOperator::Sub : BinaryOperator::Add, Shl, Op0); } Thanks, Michael

...Val + 1; >> APInt Minus1 = *IVal - 1; >> int isPow2 = Plus1.isPowerOf2() ? 1 : Minus1.isPowerOf2() ? -1 : 0; >> >> if (isPow2) { >> APInt &Pow2 = isPow2 > 0 ? Plus1 : Minus1; >> Value *Shl = Builder.CreateShl(Op0, Pow2.logBase2()); >> return BinaryOperator::Create(isPow2 > 0 ? BinaryOperator::Sub : >> BinaryOperator::Add, Shl, Op0); >> } >> >> Thanks, >> Michael >> _______________________________________________ >> LLVM Developers mailing list >> llvm-dev at lists.llvm.org >> http://lists.l...

...int isPow2 = Plus1.isPowerOf2() ? 1 : Minus1.isPowerOf2() ? > -1 : 0; > > if (isPow2) { > APInt &Pow2 = isPow2 > 0 ? Plus1 : Minus1; > Value *Shl = Builder.CreateShl(Op0, Pow2.logBase2()); > return BinaryOperator::Create(isPow2 > 0 ? > BinaryOperator::Sub : > BinaryOperator::Add, Shl, Op0); > } > > Thanks, > Michael > _______________________________________________ > LLVM Developers mailing li...

...rOf2() ? 1 : Minus1.isPowerOf2() ? > > -1 : 0; > > > > if (isPow2) { > > APInt &Pow2 = isPow2 > 0 ? Plus1 : Minus1; > > Value *Shl = Builder.CreateShl(Op0, Pow2.logBase2()); > > return BinaryOperator::Create(isPow2 > 0 ? > > BinaryOperator::Sub : > > BinaryOperator::Add, Shl, Op0); > > } > > > > Thanks, > > Michael -------------- next part -------------- An HTML attachment was scrubbed... URL...

On Thu, Dec 10, 2009 at 12:46 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > Eli, >  I have a simple SplitVecRes function that implements what you mentioned, splitting the LHS just as in BinaryOp, but passing through the RHS. The problem is that the second operand is MVT::Other, but when casted to an VTSDNode reveals that it is a vector length of the same size as the LHS

Hello, using the LLVM API, I've build one very simple function that adds two ConstantInts and returns the result. I noticed that, when I emit IR code, it is optimized to a simple "ret i16 42" when I add 40 and 2. I'd like to see the operations that are necessary to compute the result, though. Can I somehow disable this optimization in the pass, leading to more verbose IR code?

instcombine can handle certain orders of "icmp"s that are "or"ed together: x != 5 OR x > 10 OR x == 8 becomes.. x != 5 OR x == 8 becomes.. x != 5 However, a different ordering prevents the simplification: x == 8 OR x > 10 OR x != 5 becomes.. %or.eq8.gt10 OR x != 5 and that can't be simplified because we now have an "or" OR "icmp". What would I

...-1 : 0; >> > >> > if (isPow2) { >> > APInt &Pow2 = isPow2 > 0 ? Plus1 : Minus1; >> > Value *Shl = Builder.CreateShl(Op0, >> Pow2.logBase2()); >> > return BinaryOperator::Create(isPow2 > 0 ? >> > BinaryOperator::Sub : >> > BinaryOperator::Add, Shl, Op0); >> > } >> > >> > Thanks, >> > Michael >> >

Hi, From the file HowToUseJIT.cpp, I learned how to insert some calcuation IR code like Add/Sub/Mul etc by using Instruction *Add = BinaryOperator::createAdd(One, ArgX, "addresult", BB); By following this way, it works well when I insert some IR code whose operand is integer type like IntTy, however, when I tried to insert similar thing whose operands are float point, I got the following message when I run it void llvm::Binary...

On Mon, Jul 24, 2017 at 2:29 PM, John Regehr via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On 7/24/17 3:16 PM, Hongbin Zheng via llvm-dev wrote: > >> Thanks, maybe we could use ScalarEvolution in LazyValueInfo if it is >> available? >> > > This should be fairly easy to try, if you want to propose a patch and run > some experiments. The question is

Eli, I don't see how this helps with the splitting of the Other node as it isn't the Dest that is the problem, but the second source value. Any place in the code that I can look at on how to split a VTSDNode? Thanks, Micah > -----Original Message----- > From: Eli Friedman [mailto:eli.friedman at gmail.com] > Sent: Thursday, December 10, 2009 1:25 PM > To: Villmow, Micah

Here's an initial stab, but I'm not too happy about the temporarily adding new instructions then removing it because returning it will have it added back in to replace other uses. I also added a couple test cases pass with the new InstructionCombining changes (the old code only passes one of the added tests). Also, this change exposes some simplification for

Eli, I have a simple SplitVecRes function that implements what you mentioned, splitting the LHS just as in BinaryOp, but passing through the RHS. The problem is that the second operand is MVT::Other, but when casted to an VTSDNode reveals that it is a vector length of the same size as the LHS SDValue. This causes a split on the LHS side to work correctly, but then it fails instruction selection

...-1 : 0; >> > >> > if (isPow2) { >> > APInt &Pow2 = isPow2 > 0 ? Plus1 : Minus1; >> > Value *Shl = Builder.CreateShl(Op0, >> Pow2.logBase2()); >> > return BinaryOperator::Create(isPow2 > 0 ? >> > BinaryOperator::Sub : >> > BinaryOperator::Add, Shl, Op0); >> > } >> > >> > Thanks, >> > Michael >> > _________________...

IRBuilder is a templated class, and one of the template arguments is the constant folder to use. By default it uses the ConstantFolder class which does target-independant constant folding. If you want to disable constant folding you can specify the NoFolder class instead, i.e. declare the builder as follows: IRBuilder<true, llvm::NoFolder> builder(body) On 26 Nov 2013, at 19:23, Daniel

Hi... I'm having some trouble with an IR instruction. I'm triying to modify it. I was trying to create a BinaryOperator "op" with some operands from Instruction "inst": op = BinaryOperator::Create(Instruction::Add,cast<Value>(inst->getOperand(0)),cast<Value>(r),inst->getNameStr(),inst); But when executed, my pass throw a segfault and a stacktrace: ../build/Release/bin/cla...