search for: binaryop

...> : Instruction { let Namespace = "AMDIL"; dag OutOperandList = outs; dag InOperandList = ins; ILOpCode operation = op; let Pattern = pattern; let AsmString = !strconcat(asmstr, "\n"); bit hasIEEEFlag = 0; bit hasZeroOpFlag = 0; } class BinaryOp<ILOpCode op, SDNode OpNode, RegisterClass dReg, RegisterClass sReg0, RegisterClass sReg1> : ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, sReg1:$src1), !strconcat(op.Text, " $dst, $src0, $src1"), [(set dReg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>;...

...> : Instruction { let Namespace = "AMDIL"; dag OutOperandList = outs; dag InOperandList = ins; ILOpCode operation = op; let Pattern = pattern; let AsmString = !strconcat(asmstr, "\n"); bit hasIEEEFlag = 0; bit hasZeroOpFlag = 0; } class BinaryOp<ILOpCode op, SDNode OpNode, RegisterClass dReg, RegisterClass sReg0, RegisterClass sReg1> : ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, sReg1:$src1), !strconcat(op.Text, " $dst, $src0, $src1"), [(set dReg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>;...

...ot;AMDIL"; > dag OutOperandList = outs; > dag InOperandList = ins; > ILOpCode operation = op; > let Pattern = pattern; > let AsmString = !strconcat(asmstr, "\n"); > bit hasIEEEFlag = 0; > bit hasZeroOpFlag = 0; > } > class BinaryOp<ILOpCode op, SDNode OpNode, RegisterClass dReg, > RegisterClass sReg0, RegisterClass sReg1> > : ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, sReg1:$src1), > !strconcat(op.Text, " $dst, $src0, $src1"), > [(set dReg:$dst, (OpNode sReg0:$src0,...

...ot;AMDIL"; > dag OutOperandList = outs; > dag InOperandList = ins; > ILOpCode operation = op; > let Pattern = pattern; > let AsmString = !strconcat(asmstr, "\n"); > bit hasIEEEFlag = 0; > bit hasZeroOpFlag = 0; > } > class BinaryOp<ILOpCode op, SDNode OpNode, RegisterClass dReg, > RegisterClass sReg0, RegisterClass sReg1> > : ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, sReg1:$src1), > !strconcat(op.Text, " $dst, $src0, $src1"), > [(set dReg:$dst, (OpNode sReg0:$src0,...

Hi, I am working on PR34474 and try to add a new optimization to InstCombine. Like in other parts of the visitMul function I add a Shl through the IR builder and create a new BinaryOp which I return from visitMul. If I understand correctly the new BinaryOp returned from visitMul should replace the original Instruction in the Worklist. However, I end up in an infinite loop and the Instruction I try to replace gets scheduled again and again. What is wrong in my code? // Repla...

...aidl, Michael via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > >> Hi, >> >> I am working on PR34474 and try to add a new optimization to >> InstCombine. Like in other parts of the visitMul function I add a Shl >> through the IR builder and create a new BinaryOp which I return from >> visitMul. If I understand correctly the new BinaryOp returned from >> visitMul should replace the original Instruction in the Worklist. >> However, I end up in an infinite loop and the Instruction I try to >> replace gets scheduled again and again. Wha...

...sts.llvm.org>> wrote: > > Hi, > > I am working on PR34474 and try to add a new optimization to > InstCombine. Like in other parts of the visitMul function I > add a Shl > through the IR builder and create a new BinaryOp which I > return from > visitMul. If I understand correctly the new BinaryOp > returned from > visitMul should replace the original Instruction in the > Worklist. > However, I end up in an infinite loop and th...

...> > > Hi, > > > > I am working on PR34474 and try to add a new optimization to > > InstCombine. Like in other parts of the visitMul function I > > add a Shl > > through the IR builder and create a new BinaryOp which I > > return from > > visitMul. If I understand correctly the new BinaryOp > > returned from > > visitMul should replace the original Instruction in the > > Worklist. > > However, I end...

On Thu, Dec 10, 2009 at 12:46 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > Eli, >  I have a simple SplitVecRes function that implements what you mentioned, splitting the LHS just as in BinaryOp, but passing through the RHS. The problem is that the second operand is MVT::Other, but when casted to an VTSDNode reveals that it is a vector length of the same size as the LHS SDValue. This causes a split on the LHS side to work correctly, but then it fails instruction selection because of Other....

...oo", functionType, nullptr)); llvmFunction->setCallingConv(llvm::CallingConv::C); llvm::BasicBlock * body = llvm::BasicBlock::Create(c, "__entry__", llvmFunction); llvm::IRBuilder <> builder(body); llvm::Value * result = builder.CreateBinOp(llvm::Instruction::BinaryOps::Add, llvm::ConstantInt::getSigned(functionType, 40), llvm::ConstantInt::getSigned(functionType, 2)); builder.CreateRet(result); llvm::verifyModule(module, llvm::PrintMessageAction); std::string errorInfo; llvm::raw_fd_ostream fileStream("test.ll", errorInfo); llvm...

...e simplification: x == 8 OR x > 10 OR x != 5 becomes.. %or.eq8.gt10 OR x != 5 and that can't be simplified because we now have an "or" OR "icmp". What would I need to implement to restore the commutative property? Perhaps a first stab would be to take (A|B)|C create two binaryOp A|C and B|C and recursively call visitOr on each of them to see if they simplify. Using the example above.. Before: %or.eq8.gt10 = .. ; [uses=1] %res = or %or.eq8.gt10, %ne5 ; original instruction After: %or.eq8.gt10 = .. ; [uses=0] %or.eq8.ne5 = %ne5 ; instcombine recursively simplified this [us...

...I am working on PR34474 and try to add a new >> optimization to >> > InstCombine. Like in other parts of the visitMul >> function I >> > add a Shl >> > through the IR builder and create a new BinaryOp which I >> > return from >> > visitMul. If I understand correctly the new BinaryOp >> > returned from >> > visitMul should replace the original Instruction in the >> > Workli...

Hi, From the file HowToUseJIT.cpp, I learned how to insert some calcuation IR code like Add/Sub/Mul etc by using Instruction *Add = BinaryOperator::createAdd(One, ArgX, "addresult", BB); By following this way, it works well when I insert some IR code whose operand is integer type like IntTy, however, when I tried to insert similar thing whose operands are float point, I got the following message when I run it void llvm::Bina...

On Mon, Jul 24, 2017 at 2:29 PM, John Regehr via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On 7/24/17 3:16 PM, Hongbin Zheng via llvm-dev wrote: > >> Thanks, maybe we could use ScalarEvolution in LazyValueInfo if it is >> available? >> > > This should be fairly easy to try, if you want to propose a patch and run > some experiments. The question is

...Re: [LLVMdev] SplitVecRes with SIGN_EXTEND_INREG unsupported > > On Thu, Dec 10, 2009 at 12:46 PM, Villmow, Micah > <Micah.Villmow at amd.com> wrote: > > Eli, > >  I have a simple SplitVecRes function that implements what you > mentioned, splitting the LHS just as in BinaryOp, but passing through > the RHS. The problem is that the second operand is MVT::Other, but when > casted to an VTSDNode reveals that it is a vector length of the same > size as the LHS SDValue. This causes a split on the LHS side to work > correctly, but then it fails instruction selecti...

...x > 10 OR x != 5 becomes.. > %or.eq8.gt10 OR x != 5 > and that can't be simplified because we now have an "or" OR "icmp". > > What would I need to implement to restore the commutative property? > > Perhaps a first stab would be to take (A|B)|C create two binaryOp A|C > and B|C and recursively call visitOr on each of them to see if they > simplify. Using the example above.. > > Before: > %or.eq8.gt10 = .. ; [uses=1] > %res = or %or.eq8.gt10, %ne5 ; original instruction > > After: > %or.eq8.gt10 = .. ; [uses=0] > %or.eq8.ne5 = %n...

Eli, I have a simple SplitVecRes function that implements what you mentioned, splitting the LHS just as in BinaryOp, but passing through the RHS. The problem is that the second operand is MVT::Other, but when casted to an VTSDNode reveals that it is a vector length of the same size as the LHS SDValue. This causes a split on the LHS side to work correctly, but then it fails instruction selection because of Other....

...I am working on PR34474 and try to add a new >> optimization to >> > InstCombine. Like in other parts of the visitMul >> function I >> > add a Shl >> > through the IR builder and create a new BinaryOp which I >> > return from >> > visitMul. If I understand correctly the new BinaryOp >> > returned from >> > visitMul should replace the original Instruction in the >> > Workli...

...llptr)); > llvmFunction->setCallingConv(llvm::CallingConv::C); > llvm::BasicBlock * body = llvm::BasicBlock::Create(c, "__entry__", > llvmFunction); > llvm::IRBuilder <> builder(body); > llvm::Value * result = > builder.CreateBinOp(llvm::Instruction::BinaryOps::Add, > llvm::ConstantInt::getSigned(functionType, 40), > llvm::ConstantInt::getSigned(functionType, 2)); > builder.CreateRet(result); > > llvm::verifyModule(module, llvm::PrintMessageAction); > > std::string errorInfo; > llvm::raw_fd_ostream fileStream("...

Hi... I'm having some trouble with an IR instruction. I'm triying to modify it. I was trying to create a BinaryOperator "op" with some operands from Instruction "inst": op = BinaryOperator::Create(Instruction::Add,cast<Value>(inst->getOperand(0)),cast<Value>(r),inst->getNameStr(),inst); But when executed, my pass throw a segfault and a stacktrace: ../build/Release/bin/c...