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On Tue, Sep 9, 2014 at 11:39 PM, Chandler Carruth <chandlerc at google.com> wrote: > Awesome, thanks for all the information! > > See below: > > On Tue, Sep 9, 2014 at 6:13 AM, Andrea Di Biagio <andrea.dibiagio at gmail.com> > wrote: >> >> You have already mentioned how the new shuffle lowering is missing >> some features; for example, you explicitly said that we currently lack >> of SSE4.1 blend support. Unfortunately, this seems to be one of the >>...

...o MipsISelLowering.cpp. As your words,   @llvm.convert.to.fp16  can compile successfully. However, the runtime is not right. +  setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);+  setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand); Robin yalong at multicorewareinc.com  From: Andrea Di BiagioDate: 2014-07-09 14:20To: Matt ArsenaultCC: yalong at multicorewareinc.com; Kevin Qin; llvmdevSubject: Re: [LLVMdev] Help!!!!Help!!!! " LLVM ERROR: Cannot select: 0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] " problem!!!!!!!!!!!!!!!!!!Not sure if this can help, but if you really really...

+Ahmed > On Mar 2, 2018, at 6:42 AM, Andrea Di Biagio <andrea.dibiagio at gmail.com> wrote: > > There are a number of people on llvm-dev who can explain better than I how to decompile into MachineInstrs. I’m not totally opposed to checking in something that works with MCInstr, but this does run strongly contrary to the design of LLVM’s su...

Hi Andrea, So does this definition make sense for basic blocks with more than one instructions? E.g. how should one interpret a basic block with RThroughput of 2.3? On Fri, Jun 7, 2019 at 7:39 AM Andrea Di Biagio <andrea.dibiagio at gmail.com> wrote: > Hi Tom, > > Field 'Total Cycles' from the summary view simply reports the elapsed > number of cycles for the entire simulation. > > Rthroughput (from the "Instruction Info" view) is the reciprocal of the > instruc...

...// Both the fadd and the insert element below should be matched into %4 = insertelement <4 x float> %A, float %3, i32 0 // an ADDSS which does an ADD and a BLEND in one instruction. ret <4 x float> %4 } Thanks, Nadav On Dec 5, 2013, at 7:35 AM, Andrea Di Biagio <andrea.dibiagio at gmail.com> wrote: > Hi all, > > I noticed that the x86 backend tends to emit unnecessary vector insert > instructions immediately after sse scalar fp instructions like > addss/mulss. > > For example: > ///////////////////////////////// > __m12...

+1 Thanks Nadav for your help over the last few years! Andrea On Mon, Nov 7, 2016 at 9:20 PM, Matthew Simpson via llvm-dev < llvm-dev at lists.llvm.org> wrote: > +1 > > -- Matt > > On Sun, Nov 6, 2016 at 1:00 AM, Nadav Rotem via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > >> It been a while since I worked on the vectorizers and I think that it's

...t the ability of a pass like this to pattern match specific sequences of instructions. In conclusion, my questions are: Would a patch be acceptable that introduces a new MachineFunctionPass that runs at 'postRegAlloc' stage? If not, is there a better way to fix this bug? Thanks, Andrea Di Biagio SN Systems - Sony Computer Entertainment Group -------------- next part -------------- Index: lib/Target/X86/X86.h =================================================================== --- lib/Target/X86/X86.h (revision 196508) +++ lib/Target/X86/X86.h (working copy) @@ -47,6 +47,8 @@ /// FunctionP...

Hi Chandler, I have tested the new shuffle lowering on a AMD Jaguar cpu (which is AVX but not AVX2). On this particular target, there is a delay when output data from an execution unit is used as input to another execution unit of a different cluster. For example, There are 6 executions units which are divided into 3 execution clusters of Float(FPM,FPA), Vector Integer (MMXA,MMXB,IMM), and Store

I ran the benchmarking subset of test-suite on a btver2 machine and optimizing for btver2 (so enabling AVX codegen). I don't see anything outside of the noise with x86-experimental-vector-shuffle-legality=1. On Fri, Jan 23, 2015 at 5:19 AM, Andrea Di Biagio <andrea.dibiagio at gmail.com > wrote: > Hi Chandler, > > On Fri, Jan 23, 2015 at 8:15 AM, Chandler Carruth <chandlerc at gmail.com> > wrote: > > Greetings LLVM hackers and x86 vector shufflers! > > > > I would like to flip on another chunk of the new vect...

...compilation part (based on LLVM), a distributed runtime system, and a set of advanced modeling approaches. The programming model is based on SYCL, the compilation infrastructure will use LLVM on SPIR-V kernels. For full details please see: http://www.aes.tu-berlin.de/menue/jobs/ Best regards, Biagio Cosenza -- Biagio Cosenza, PhD Senior Researcher Technische Universität Berlin Fakultät IV - Elektrotechnik und Informatik Institut für Technische Informatik und Mikroelektronik (TIME) Architektur eingebetteter Systeme (AES) EN 12/ Raum EN 636, Einsteinufer 17, 10587 Berlin, Germany Telefon: +4...

...ion logic in class ResourceManager (in llvm-mca) would require a bit of refactoring. Other than that, the rest should be doable. -Andrea > > -Alex > On May 10, 2020, 9:32 AM -0400, Andrew Trick <atrick at apple.com>, wrote: > > > > On May 9, 2020, at 5:12 PM, Andrea Di Biagio via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > The llvm scheduling model is quite simple and doesn't allow mca to > accurately simulate the execution of individual uOPs. That limitation is > sort-of acceptable if you consider how the scheduling model framework was...

Wow. Somehow, I forgot about vbroadcast and vpbroadcast. =[ Sorry about that. I'll fix those. On Fri, Sep 26, 2014 at 3:39 AM, Andrea Di Biagio <andrea.dibiagio at gmail.com > wrote: > Hi Chandler, > > Here is another test. > > When looking at the AVX codegen, I noticed that, when using the new > shuffle lowering, we no longer emit a single vbroadcastss in the case > where the shuffle performs a splat of a scala...

> On May 11, 2018, at 4:26 AM, Andrea Di Biagio <andrea.dibiagio at gmail.com> wrote: > > The goal is to help users defining a predicate the check logic. If we use a TIIPredicate, we specify the logic only once, in a declarative way, and then we let tablegen generate code for us. > > If for some reason, a user doesn't wan...

Hi Andrea, On Mon, Dec 03, 2018 at 01:21:33PM +0000, Andrea Di Biagio wrote: > So, I have been thinking a bit more about this whole design. > > The more I think about your suggested design, the more I am convinced that > we should do something more to support ranges in binary object files too. > My understanding is that the reason why we don't sup...

...er. (NOTE: this constraint can be removed). 4) Add clang tests: * in test/Sema: ** Verify that noopt only applies to functions. (-cc1 -fsyntax-only -verify) * in test/CodeGen: ** Check that noopt implies noinline ** Check combinations of noopt and noinline and always_inline Andrea Di Biagio SN Systems - Sony Computer Entertainment Group. Andrea DiBiagio/SN R&D/BS/UK/SCEE wrote on 25/06/2013 15:20:12: > From: Andrea DiBiagio/SN R&D/BS/UK/SCEE > To: Nick Lewycky <nicholas at mxc.ca> > Cc: cfe-dev at cs.uiuc.edu, llvmdev at cs.uiuc.edu > Date: 25/06/2013 15:20...

...bility required by 'optnone'. It seems it would either require some modifications to the Pass Manager or we would have to make individual passes aware of the attribute. Neither of these solutions seem particularly attractive to me, so I'm open to any suggestions! Thanks, Andrea Di Biagio SN Systems - Sony Computer Entertainment Group ********************************************************************** This email and any files transmitted with it are confidential and intended solely for the use of the individual or entity to whom they are addressed. If you have received this e...

...anches, then we can remove this constraint. > > -Matt > > > -----Original Message----- > > From: llvm-dev <llvm-dev-bounces at lists.llvm.org> On Behalf Of Matt > Davis via llvm- > > dev > > Sent: Wednesday, November 21, 2018 8:47 AM > > To: Andrea Di Biagio <andrea.dibiagio at gmail.com> > > Cc: llvm-dev <llvm-dev at lists.llvm.org>; Di Biagio, Andrea > > <Andrea.Dibiagio at sony.com>; cfe-dev at lists.llvm.org > > Subject: Re: [llvm-dev] [RFC][llvm-mca] Adding binary support to > llvm-mca. > > > > Hi...

> On Mar 6, 2018, at 4:20 AM, Andrea Di Biagio <andrea.dibiagio at gmail.com> wrote: > > To be clear then, resolveSchedClass should be moved from TargetSchedModel into MCSchedModel (which is where I originally wanted it). Any TargetInstrInfo APIs called from SchedPredicate should be moved to MCInstrInfo, which should be straightfor...

..., I would advocate for > experimental intrinsics unless people can contribute other example use > cases. > > On Mon, Dec 3, 2018 at 11:38 PM Matt Davis <matthew.davis at sony.com> wrote: > >> Hi Andrea, >> >> On Mon, Dec 03, 2018 at 01:21:33PM +0000, Andrea Di Biagio wrote: >> > So, I have been thinking a bit more about this whole design. >> > >> > The more I think about your suggested design, the more I am convinced >> that >> > we should do something more to support ranges in binary object files >> too. >>...

On Wed, Apr 24, 2013 at 6:00 AM, <Andrea_DiBiagio at sn.scee.net> wrote: > Hello, > > We've had a high priority feature request from a number of our customers > to > provide per-function optimization in our Clang/LLVM compiler. > I would be interested in working with the community to implement this. > The idea is to al...