search for: bcs54_d

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2015 Jun 26
2
[LLVMdev] Can LLVM vectorize <2 x i32> type
...1> %end.idxS51_D = add <2 x i64> %S49_D, <i64 1, i64 1> %n.vecS52_D = and <2 x i64> %S50_D, <i64 8589934584, i64 8589934584> %cmp.zeroS53_D = icmp eq <2 x i64> %n.vecS52_D, zeroinitializer %sextS54_D = sext <2 x i1> %cmp.zeroS53_D to <2 x i64> %BCS54_D = bitcast <2 x i64> %sextS54_D to i128 %mskS54_D = icmp ne i128 %BCS54_D, 0 br i1 %mskS54_D, label %middle.block, label %vector.ph Now the assembly for the above IR code is: # BB#4: # %for.cond.preheader vmovdqa 144(%rsp), %xmm0 # 16-byte Reload...
2015 Jun 24
2
[LLVMdev] Can LLVM vectorize <2 x i32> type
Hi, Is LLVM be able to generate code for the following code? %mul = mul <2 x i32> %1, %2, where %1 and %2 are <2 x i32> type. I am running it on a Haswell processor with LLVM-3.4.2. It seems that it will generates really complicated code with vpaddq, vpmuludq, vpsllq, vpsrlq. Thanks, Zhi -------------- next part -------------- An HTML attachment was scrubbed... URL: