Displaying 2 results from an estimated 2 matches for "bcs46_d".
2015 Jun 26
2
[LLVMdev] Can LLVM vectorize <2 x i32> type
...he following
for.cond.preheader: ; preds = %if.end18
%mulS44_D = mul <2 x i32> %splatLDS24_D.splat, %splatLDS7_D.splat
%cmp21128S45_D = icmp sgt <2 x i32> %mulS44_D, zeroinitializer
%sextS46_D = sext <2 x i1> %cmp21128S45_D to <2 x i64>
%BCS46_D = bitcast <2 x i64> %sextS46_D to i128
%mskS46_D = icmp ne i128 %BCS46_D, 0
br i1 %mskS46_D, label %for.body.preheader, label %return
for.body.preheader: ; preds =
%for.cond.preheader
%S47_D = mul <2 x i32> %splatLDS24_D.splat, %splatLDS7_D.splat
%...
2015 Jun 24
2
[LLVMdev] Can LLVM vectorize <2 x i32> type
Hi,
Is LLVM be able to generate code for the following code?
%mul = mul <2 x i32> %1, %2, where %1 and %2 are <2 x i32> type.
I am running it on a Haswell processor with LLVM-3.4.2. It seems that it
will generates really complicated code with vpaddq, vpmuludq, vpsllq,
vpsrlq.
Thanks,
Zhi
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