search for: baseaddr

...ons. Gather/scatter instructions allow read/write access to multiple memory addresses. The addresses are specified using a base address and a vector of indices. We'd like Vectorizers to tap this functionality, and propose to do so by introducing new intrinsics: VectorValue = @llvm.sindex.load (BaseAddr, VectorOfIndices, Scale) VectorValue = @llvm.uindex.load (BaseAddr, VectorOfIndices, Scale) VectorValue = @llvm.sindex.masked.load (BaseAddr, VectorOfIndices, Scale, PassThruVal, Mask) VectorValue = @llvm.uindex.masked.load (BaseAddr, VectorOfIndices, Scale, PassThruVal, Mask) Semantics: For i=0,1...

...ions allow read/write access to multiple memory > addresses. The addresses are specified using a base address and a > vector of indices. > We’d like Vectorizers to tap this functionality, and propose to do so > by introducing new intrinsics: > > VectorValue = @llvm.sindex.load (BaseAddr, VectorOfIndices, Scale) > VectorValue = @llvm.uindex.load (BaseAddr, VectorOfIndices, Scale) > VectorValue = @llvm.sindex.masked.load (BaseAddr, VectorOfIndices, > Scale, PassThruVal, Mask) VectorValue = @llvm.uindex.masked.load > (BaseAddr, VectorOfIndices, Scale, PassThruVal, Mas...

...)) { LPVOID v = (LPVOID)NULL; DWORD r, old_protection = 0; MEMORY_BASIC_INFORMATION basic_info; printf("Original EXE loaded (PID = %d).\n", (int)pi.dwProcessId); printf("Original Base Addr = %X, Size = %X\n", (int)childInfo.baseAddr, (int)childInfo.imageSize); if (VirtualQueryEx( pi.hProcess, (LPCVOID)childInfo.baseAddr, &basic_info, sizeof(MEMORY_BASIC_INFORMATION)) == 0) { ErrorExit("VirtualQueryEx: Failed!\n"); TerminateProcess(pi...

On 12/18/2014 11:56 AM, dag at cray.com wrote: > "Demikhovsky, Elena" <elena.demikhovsky at intel.com> writes: > >> Semantics: >> For i=0,1,…,N-1: if (Mask[i]) {*(BaseAddr + VectorOfIndices[i]*Scale) >> = VectorValue[i];} >> VectorValue: any float or integer vector type. >> BaseAddr: a pointer; may be zero if full address is placed in the >> index. >> VectorOfIndices: a vector of i32 or i64 signed or unsigned integer >> values. &gt...

...bject: Re: [LLVMdev] Indexed Load and Store Intrinsics - proposal > > > On 12/18/2014 11:56 AM, dag at cray.com wrote: > > "Demikhovsky, Elena" <elena.demikhovsky at intel.com> writes: > > > >> Semantics: > >> For i=0,1,…,N-1: if (Mask[i]) {*(BaseAddr + > >> VectorOfIndices[i]*Scale) > >> = VectorValue[i];} > >> VectorValue: any float or integer vector type. > >> BaseAddr: a pointer; may be zero if full address is placed in the > >> index. > >> VectorOfIndices: a vector of i32 or i64 signed o...

...gt; + E820Map = Info->E820; > + for (Loop = 0; Loop < Info->E820EntryCount; Loop++) { > + Entry = E820Map + Loop; > + > + // only care about RAM > + if (Entry->Type != EfiAcpiAddressRangeMemory) > + continue; > + > + if (Entry->BaseAddr >= BASE_4GB) > + AddUntestedMemoryBaseSizeHob (Entry->BaseAddr, Entry->Length); > + else > + AddMemoryBaseSizeHob (Entry->BaseAddr, Entry->Length); > + > + MtrrSetMemoryAttribute (Entry->BaseAddr, Entry->Length, CacheWriteBack); > +...

...rameter. Be aware that using incorrect parameters (base + address in particular) can crash your system - you have been warned. + + The format for the parameter is as follows: + + [virtio_mmio.]devices=<device>[<delim><device>] + + where: + <device> := <size>@<baseaddr>:<irq> + <delim> := ',' or ';' + <size> := size (can use standard suffixes like K or M) + <baseaddr> := physical base address + <irq> := interrupt number (as passed to request_irq()) + + Example kernel command line parameter: + + vi...

...rameter. Be aware that using incorrect parameters (base + address in particular) can crash your system - you have been warned. + + The format for the parameter is as follows: + + [virtio_mmio.]devices=<device>[<delim><device>] + + where: + <device> := <size>@<baseaddr>:<irq> + <delim> := ',' or ';' + <size> := size (can use standard suffixes like K or M) + <baseaddr> := physical base address + <irq> := interrupt number (as passed to request_irq()) + + Example kernel command line parameter: + + vi...

...nd Store Intrinsics - proposal > > > > > > On 12/18/2014 11:56 AM, dag at cray.com wrote: > > > "Demikhovsky, Elena" <elena.demikhovsky at intel.com> writes: > > > > > >> Semantics: > > >> For i=0,1,…,N-1: if (Mask[i]) {*(BaseAddr + > > >> VectorOfIndices[i]*Scale) > > >> = VectorValue[i];} > > >> VectorValue: any float or integer vector type. > > >> BaseAddr: a pointer; may be zero if full address is placed in > > >> the > > >> index. > > >>...

...tchdog support is enabled. @@ -2847,6 +2848,22 @@ bytes respectively. Such letter suffixes can also be entirely omitted. video= [FB] Frame buffer configuration See Documentation/fb/modedb.txt. + virtio_mmio.device= + [VMMIO] Memory mapped virtio (platform) device. + + <size>@<baseaddr>:<irq>[:<id>] + where: + <size> := size (can use standard suffixes + like K, M and G) + <baseaddr> := physical base address + <irq> := interrupt number (as passed to + request_irq()) + <id> := (optional) platform device i...

...tchdog support is enabled. @@ -2847,6 +2848,22 @@ bytes respectively. Such letter suffixes can also be entirely omitted. video= [FB] Frame buffer configuration See Documentation/fb/modedb.txt. + virtio_mmio.device= + [VMMIO] Memory mapped virtio (platform) device. + + <size>@<baseaddr>:<irq>[:<id>] + where: + <size> := size (can use standard suffixes + like K, M and G) + <baseaddr> := physical base address + <irq> := interrupt number (as passed to + request_irq()) + <id> := (optional) platform device i...

I run this prog (http://www.compcar.ru/forum/showthread.php?t=7342)and this error appears: Fatal error occurred in main thread. Address:0x004a1f11 Exception:0xc0000005 I added every library whitch Igo needed (native-builtin) / I found them by Ollydebuger in Windows 7/ , but no success :( Could I add some other info to solve this?

Very soon Guild Wars 2, the MMO we've all been waiting for (right? right!) is coming, and I would like to do my part to make sure that it runs under Wine from day one. Especially as GW1 is one of the top-performing games under Wine. Now I am not an avid coder, but I will pre-purchase the CE, and with it comes access to all the beta events between April 10 and release. So there should be

> Of course, and the point is that, for example, on x86_64, the zext here is free. I'm still trying to understand the problem... > > In the example you provided in your previous e-mail, we choose the solution: > > `GEP @Global, zext(V)` -> `GEP (@Global + zext VStart), {i64 0,+,1}` > `V` -> `trunc({i64 0,+,1}) + VStart` > > instead of the actually-better

...lib/Analysis/ScopInfo.cpp (revision 144978) > +++ lib/Analysis/ScopInfo.cpp (working copy) > @@ -311,29 +311,38 @@ > Type = Access.isRead() ? Read : Write; > statement = Statement; > > - isl_pw_aff *Affine = SCEVAffinator::getPwAff(Statement, Access.getOffset()); > BaseAddr = Access.getBase(); > > - setBaseName(); > + if (Access.isAffine()) { > > - // Devide the access function by the size of the elements in the array. > - // > - // A stride one array access in C expressed as A[i] is expressed in LLVM-IR > - // as something like A[i * ele...

...opInfo.h 2011-11-13 02:34:47.000000000 +0100 > @@ -45,12 +45,13 @@ > private: > unsigned ElemBytes; > TypeKind Type; > + bool is_affine; I think IsAffine matches more the LLVM coding conventions. > > public: > explicit IRAccess (TypeKind Type, const Value *BaseAddress, > - const SCEV *Offset, unsigned elemBytes) > + const SCEV *Offset, unsigned elemBytes, bool affine) 'affine' should start with an uppercase letter. Polly itself has some inconsistent naming, but we started to follow the LLVM coding conve...

2011/11/15 Marcello Maggioni <hayarms at gmail.com>: > 2011/11/14 Tobias Grosser <tobias at grosser.es>: >> On 11/14/2011 02:45 PM, Marcello Maggioni wrote: >>> >>> 2011/11/14 Tobias Grosser<tobias at grosser.es>: >>>> >>>> On 11/14/2011 01:24 AM, Marcello Maggioni wrote: >>>>> >>>>> Hi Tobias.

...144978) >> +++ lib/Analysis/ScopInfo.cpp   (working copy) >> @@ -311,29 +311,38 @@ >>    Type = Access.isRead() ? Read : Write; >>    statement = Statement; >> >> -  isl_pw_aff *Affine = SCEVAffinator::getPwAff(Statement, >> Access.getOffset()); >>    BaseAddr = Access.getBase(); >> >> -  setBaseName(); >> +  if (Access.isAffine()) { >> >> -  // Devide the access function by the size of the elements in the array. >> -  // >> -  // A stride one array access in C expressed as A[i] is expressed in >> LLVM-IR &...

I have a new problem: Register RBP is used in a function foo. (I am not allocating RBP to any virtual register, the instances of RBP in function foo are in the machine code when my register allocator starts.) Function foo calls function bar. Register RBP is not saved across the call, though it is live after the call. Function bar includes a virtual register. The code that I'm using to

...; chk[tblend + i] = jamstate; } jambase = tblend; base[jamstate] = jambase; def[jamstate] = 0; tblend += numecs; ++numtemps; } void mkentry( state, numchars, statenum, deflink, totaltrans ) register int *state; int numchars, statenum, deflink, totaltrans; { register int minec, maxec, i, baseaddr; int tblbase, tbllast; if ( totaltrans == 0 ) { if ( deflink == -32766 ) base[statenum] = -32766; else base[statenum] = 0; def[statenum] = deflink; return; } for ( minec = 1; minec <= numchars; ++minec ) { if ( state[minec] != -1 ) if ( state[minec] != 0 || deflink !=...