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On 02/16/2017 12:08 PM, Stephen Canon wrote: >> On Feb 16, 2017, at 9:12 AM, Bagel <bagel99 at gmail.com >> <mailto:bagel99 at gmail.com>> wrote: >> >> I figured that the optimization of this would bedifficult (else it would >> have already been done :-)) > > Don’t make this assumption. There’s lots of opportunities for optimization > scattered a...

...What IR pattern it would replace? — Mehdi > > On Fri, Feb 17, 2017 at 8:52 PM, Bagel via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: > On 02/16/2017 12:08 PM, Stephen Canon wrote: > >> On Feb 16, 2017, at 9:12 AM, Bagel <bagel99 at gmail.com <mailto:bagel99 at gmail.com> > >> <mailto:bagel99 at gmail.com <mailto:bagel99 at gmail.com>>> wrote: > >> > >> I figured that the optimization of this would bedifficult (else it would > >> have already been done :-)) > >...

It takes two "llvm.uadd.with.overflow" instances to model the add-with-carry when there is a carry-in. Look at the IR generated by the example. I figured that the optimization of this would bedifficult (else it would have already been done :-)). And would this optimization have to be done for every architecture? On 02/15/2017 04:28 PM, Stephen Canon wrote: > > Why do you think

On 23 November 2010 18:03, Bagel <bagel99 at gmail.com> wrote: > Would someone be so kind as to tell me what the status of debugging symbols > (DWARF) generated by clang/llvm is? Hi Bagel, It should be fairly complete... > When I generate an executable with "clang -g" followed by "llc -O0" and feed it &g...

On 09/11/2014 05:33 PM, Quentin Colombet wrote: > Hi Brian, > > On Sep 11, 2014, at 3:03 PM, Bagel <bagel99 at gmail.com> wrote: > >> When the IR specifies a 32 bit load can it be changed to a narrower >> load? What if the load is from memory (e.g. a peripheral) that only >> supports 32-bit access? Consider the following IR: ---- target datalayout >> = "e-p:32:32:32-i1:...

Would someone be so kind as to tell me what the status of debugging symbols (DWARF) generated by clang/llvm is? I am on a linux x86-64 system (Fedora 13). Is gdb supposed to understand the generated DWARF? When I generate an executable with "clang -g" followed by "llc -O0" and feed it to gdb, I get "no debugging symbols found". What is the status of lldb on

On 4 December 2010 21:16, bagel <bagel99 at gmail.com> wrote: > Perhaps you can add another section just on the textual format? Oh, perhaps you're looking for this: http://llvm.org/docs/SourceLevelDebugging.html cheers, --renato

On 08/20/2010 04:06 PM, Eli Friedman wrote: > On Fri, Aug 20, 2010 at 1:03 PM, Bagel<bagel99 at gmail.com> wrote: >> I propose a new intrinsic "llvm.memcmp" that compares a block of memory >> for equality (a subset of the libc behavior). Backends are free to use the >> alignment to optimize using wider than byte operations. Since the result is >> onl...

On 12/03/2010 06:28 PM, Devang Patel wrote: > We are working on a document. Here is current draft: > http://wiki.llvm.org/Debug_Information > > - > Devang While this is great news, it doesn't completely satisfy my needs. Your documentation assumes one is going to use the LLVM provided functions (such as DIFactory::). My front-end can't use them because it is not

When the IR specifies a 32 bit load can it be changed to a narrower load? What if the load is from memory (e.g. a peripheral) that only supports 32-bit access? Consider the following IR: ---- target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32" target triple = "thumbv7m-unknown-unknown" @f = external global i32 define zeroext i8 @bar() nounwind { L.0:

The following causes an assertion in recent svn pulls, but not in 2.5. The assertion: llvm-as: /home/bgl/work/llvm-work/include/llvm/ADT/SmallVector.h:125: T& llvm::SmallVectorImpl<T>::operator[](unsigned int) [with T = llvm::Constant*]: Assertion `Begin + idx < End' failed. The .ll code: target datalayout =

On Fri, Aug 20, 2010 at 1:03 PM, Bagel <bagel99 at gmail.com> wrote: > I propose a new intrinsic "llvm.memcmp" that compares a block of memory > for equality (a subset of the libc behavior).  Backends are free to use the > alignment to optimize using wider than byte operations.  Since the result is > only equal/not-equal...

I am writing a backend for an experimental machine that has both 2-address and 3-address versions of some instructions. The 2-address versions are more compact and thus preferred when applicable. How does one go about generating the most compact version? 1. At instruction selection, is there a predicate that can test whether one of the input sources is dead, thus allowing the selection of the

I propose a new intrinsic "llvm.memcmp" that compares a block of memory for equality (a subset of the libc behavior). Backends are free to use the alignment to optimize using wider than byte operations. Since the result is only equal/not-equal, byte order is not important. For languages that support array compares, this would be very useful. Syntax: declare i1 @llvm.memcmp(i8*

Any progress on the TI MSP430 target?

Now that there is good thumb2 support in the ARM backend, would someone please add "cortex-m3" to the "-march" list for the ARM backend. This should produce pure thumb2 only code. At some point, when the subsets are public, "cortex-m1" and "cortex-m0" should also be added. thanks, bagel

Here is a one-line patch to support the cortex-m3. For those who plan the features for ARM, the new cortex-m0 implements only a subset of the Thumb2 instructions. I still have yet to see a document that details what's in the subset. -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: arm.diff URL:

Looks OK to me, but I don't have any Cortex-M3 docs to confirm the choice of v7-A without NEON. deep On Sun, Nov 22, 2009 at 9:47 PM, Bagel <bagel99 at gmail.com> wrote: > Here is a one-line patch to support the cortex-m3. > For those who plan the features for ARM, the new cortex-m0 implements only a > subset of the Thumb2 instructions.  I still have yet to see a document that > details what's in the subset. > > > In...

When addresses are a displacement from a constant (this can happen in device drivers), the resulting address gets folded rather than using base+displacement addressing. This results in code bloat. Example test attached. -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: const-addr.ll URL:

I'm not authorized to file bugs. Would someone please enter this? Thank you, bagel Evan Cheng wrote: > Right. I am aware of this problem but am not sure about what to do about it. > It's common for a number 32-bit immediates in the same block with the same > lower or higher 16-bit. Since the immediates will not be split until late in > codegen, the target independent