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aginstr
2009 Jul 02
1
[LLVMdev] [Help Needed] tblgen code get a compile error
...);
return ResNode;
}
SDNode *Select_ISD_ADDC_i8(const SDValue &N) {
SDNode *Result = Emit_2(N, AVR::ADC, MVT::i8);
return Result;
}
the related defines are:
def ADC : RR<7, "adc $dst, $src2", addc>;
class RR<bits<6> opcode, string asmstr, SDNode OpNode>
: AVRInstr<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2), asmstr,
[(set GR8:$dst, (OpNode GR8:$src1, GR8:$src2)), (implicit SREG)]> {
let Inst{15-10} = opcode;
}
class AVRInstr<dag outs, dag ins, string asmstr, list<dag> pattern>
: Instruction {
field bits<16> Inst;...