Displaying 4 results from an estimated 4 matches for "aginstr".
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aginst
2012 Mar 14
2
[LLVMdev] Data/Address registers
...have no clue what is going wrong. I can't realize where register
classes are matched in order to pick the right instructions. I couldn't
find a trace of register classes in the instruction selection process.
I have these patterns defined so far:
def AADDMri { // Instruction MephInstr AGInstr
dag OutOperandList = (outs AGRegs:$dst);
dag InOperandList = (ins AGRegs:$a, i16imm:$b);
list<dag> Pattern = [(set AGRegs:$dst, (add AGRegs:$a, imm:$b))];
...
}
def DADDri { // Pattern Pat
dag PatternToMatch = (add LSubRegs:$a, imm:$b);
list<dag> ResultInstrs = [(a...
2012 Mar 14
0
[LLVMdev] Data/Address registers
...what is going wrong. I can't realize where register classes are matched in order to pick the right instructions. I couldn't find a trace of register classes in the instruction selection process.
> I have these patterns defined so far:
>
> def AADDMri { // Instruction MephInstr AGInstr
> dag OutOperandList = (outs AGRegs:$dst);
> dag InOperandList = (ins AGRegs:$a, i16imm:$b);
> list<dag> Pattern = [(set AGRegs:$dst, (add AGRegs:$a, imm:$b))];
> …
> }
>
> def DADDri { // Pattern Pat
> dag PatternToMatch = (add LSubRegs:$a, imm:$b);
> li...
2012 Mar 07
0
[LLVMdev] Data/Address registers
On Mar 7, 2012, at 6:23 AM, Ivan Llopard <ivanllopard at gmail.com> wrote:
> Hi Jim,
>
> Thanks for your response.
>
> Le 06/03/2012 22:54, Jim Grosbach a écrit :
>> Hi Ivan,
>> On Mar 3, 2012, at 4:48 AM, Ivan Llopard<ivanllopard at gmail.com> wrote:
>>
>>> Hi,
>>>
>>> I'm facing a problem in llvm while porting it
2012 Mar 07
2
[LLVMdev] Data/Address registers
Hi Jim,
Thanks for your response.
Le 06/03/2012 22:54, Jim Grosbach a écrit :
> Hi Ivan,
> On Mar 3, 2012, at 4:48 AM, Ivan Llopard<ivanllopard at gmail.com> wrote:
>
>> Hi,
>>
>> I'm facing a problem in llvm while porting it to a new target and I'll
>> need some support.
>> We have 2 kind of register, one for general purposes (i.e.