search for: avr32

From: Bradley Smith <brad at brad-smith.co.uk> This patch is from http://git.brad-smith.co.uk/?p=avr32/klibc.git;a=summary It squashes together and includes those commits: * Fix ld flags such that shared builds actually run. * Fix setjmp. * Fix sigaction/sigrestorer. * Tidy everything up. * Fix lseek mess. Cc: H?vard_Skinnemoen <hskinnemoen at gmail.com> Cc: Hans-Christian Egtvedt <hans-c...

Greetings everyone, I'm trying to compile asterisk for an AVR32 (Atmel NGW100). Buildroot for AVR32 already has the asterisk package, though it has bugs. Firstly it tries to apply a patch for 1.2 on a 1.6, but deleting the contents of the patch file did the trick. Now, the problem is making asterisk. The first error is because asterisk needed to be ./config...

Split out subsystem specific changes for easier reviews. This will be squashed with main commit. Signed-off-by: Krzysztof Kozlowski <k.kozlowski at samsung.com> --- arch/avr32/mm/dma-coherent.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/avr32/mm/dma-coherent.c b/arch/avr32/mm/dma-coherent.c index 92cf1fb2b3e6..fc51f4421933 100644 --- a/arch/avr32/mm/dma-coherent.c +++ b/arch/avr32/mm/dma-coherent.c @@ -99,7 +99,7 @@ static void __dma...

Hello, I am interested to use Speex but need to know If I can use it under our project's constraint. We need to use a low cost micro controller on a very small PCB. This means there's no space for an external DSP unit. Can someone tell me if using an AVR32 (Atmel uc) which has a floating point calculation unit and DSP instruction set and running at ~50Mhz for a narrow band 8Kbps sampling rate maybe be feasible or out of reach? AT32UC3C0512C: Low Power 32-bit AVR? Microcontroller ? Compact Single-cycle RISC Instruction Set Including DSP Instructi...

Yes, it does and thanks for the fast answer! The AVR32 runs at same speed but has a built in floating point unit for float calcs and a DSP instruction Set. But If I use the fixed point version I guess it doesn't change anything then. So another question: - Is there a difference of performance/quality between the floating point and the fixed...

Anyone else interested in an AVR backend? If so, for what members of the AVR family? If we do a port, likely it'll support only the ATmegas. John

I have a client who might well make use of an AVR32 port, but I suspect that machine is very different than the one you are currently examining. shap On Mon, 2008-05-19 at 12:38 -0600, John Regehr wrote: > Anyone else interested in an AVR backend? > > If so, for what members of the AVR family? If we do a port, likely it'll > sup...

> I have a client who might well make use of an AVR32 port, but I suspect > that machine is very different than the one you are currently examining. I have not looked at AVR32 closely but my understanding is that it is a new architecture that shares a substring with AVR for marketing reasons. John

Hello, I'm trying to use speex for implementing a VoIP demo application using linphone on an embedded system. At the moment I'm not really able to do real time encoding, and thinking about making an assembler port for speex to the AVR32 architecture. The AVR32 is a new hybrid MCU/DSP fixed point processor running at 120Mhz in my application. Does anyone have experiences/info about the computational power requirements, e.g. what quality/bitrate and complexity of encoding seem to be realistic as target operating modes. I've...

...ng it was to add a bitreverse intrinsic to llvm ir, which itself might not be the best option since bitreverse probably isn't too common. Other targets that I know of that could potentially benefit from this optimization being global (that have a clz and bitreverse instruction but not ctz) are AVR32 and C64x, neither of which llvm has backends for yet. -------------- next part -------------- A non-text attachment was scrubbed... Name: llvm-ctz-arm.diff Type: application/octet-stream Size: 5160 bytes Desc: not available URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20100115/9da...

...ed patches to fix them up. Signed-off-by: Michael S. Tsirkin <mst at redhat.com> ---------------------------------------------------------------- Michael S. Tsirkin (37): x86/uaccess: fix sparse errors alpha/uaccess: fix sparse errors arm64/uaccess: fix sparse errors avr32/uaccess: fix sparse errors blackfin/uaccess: fix sparse errors cris/uaccess: fix sparse errors ia64/uaccess: fix sparse errors m32r/uaccess: fix sparse errors metag/uaccess: fix sparse errors openrisc/uaccess: fix sparse errors parisc/uaccess: fix sparse er...

...ed patches to fix them up. Signed-off-by: Michael S. Tsirkin <mst at redhat.com> ---------------------------------------------------------------- Michael S. Tsirkin (37): x86/uaccess: fix sparse errors alpha/uaccess: fix sparse errors arm64/uaccess: fix sparse errors avr32/uaccess: fix sparse errors blackfin/uaccess: fix sparse errors cris/uaccess: fix sparse errors ia64/uaccess: fix sparse errors m32r/uaccess: fix sparse errors metag/uaccess: fix sparse errors openrisc/uaccess: fix sparse errors parisc/uaccess: fix sparse er...

I don't know the AVR32 chip. However for an ARM7TDMI running at 50 MHz, assuming a good compiler and some hand-coded assembly, you would be very close to the achievable limit (couldn't say on which side). So if your AVR32 is faster than an ARM7TDMI, it's likely achievable. If it's slower, then it's likely...

On 15 Jan 2010, at 18:03, Chris Lattner wrote: > On Jan 14, 2010, at 10:13 PM, David Conrad wrote: > >> Other targets that I know of that could potentially benefit from >> this optimization being global (that have a clz and bitreverse >> instruction but not ctz) are AVR32 and C64x, neither of which llvm >> has backends for yet. > > When/if another target wants this, we could add a ISD::RBIT operation, > it doesn't need to be added at the llvm ir level, The XCore also has ctlz and bitreverse instructions and not cttz. At the moment in the XCo...

...> probably isn't too common. I haven't looked at the patch in detail, but this approach makes sense to me. > Other targets that I know of that could potentially benefit from > this optimization being global (that have a clz and bitreverse > instruction but not ctz) are AVR32 and C64x, neither of which llvm > has backends for yet. When/if another target wants this, we could add a ISD::RBIT operation, it doesn't need to be added at the llvm ir level, -Chris

From: Matt Fleming <matt at console-pimps.org> Uncovered a bug in avr32 signal handling, might come handy in testing other archs signal. Signed-off-by: Matt Fleming <matt at console-pimps.org> Signed-off-by: maximilian attems <max at stro.at> --- Seen on lmkl, any objections to add your test to klibc: http://git.kernel.org/?p=libs/klibc/klibc.git;a=summar...

...nux at armlinux.org.uk> Signed-off-by: Christian Borntraeger <borntraeger at de.ibm.com> --- arch/alpha/include/asm/processor.h | 1 - arch/arc/include/asm/processor.h | 3 --- arch/arm/include/asm/processor.h | 2 -- arch/arm64/include/asm/processor.h | 2 -- arch/avr32/include/asm/processor.h | 1 - arch/blackfin/include/asm/processor.h | 1 - arch/c6x/include/asm/processor.h | 1 - arch/cris/include/asm/processor.h | 1 - arch/frv/include/asm/processor.h | 1 - arch/h8300/include/asm/processor.h | 1 - arch/hexagon/include/asm/pro...

...nux at armlinux.org.uk> Signed-off-by: Christian Borntraeger <borntraeger at de.ibm.com> --- arch/alpha/include/asm/processor.h | 1 - arch/arc/include/asm/processor.h | 3 --- arch/arm/include/asm/processor.h | 2 -- arch/arm64/include/asm/processor.h | 2 -- arch/avr32/include/asm/processor.h | 1 - arch/blackfin/include/asm/processor.h | 1 - arch/c6x/include/asm/processor.h | 1 - arch/cris/include/asm/processor.h | 1 - arch/frv/include/asm/processor.h | 1 - arch/h8300/include/asm/processor.h | 1 - arch/hexagon/include/asm/pro...

...remove cpu_relax_lowlatency. Signed-off-by: Christian Borntraeger <borntraeger at de.ibm.com> --- arch/alpha/include/asm/processor.h | 1 - arch/arc/include/asm/processor.h | 2 -- arch/arm/include/asm/processor.h | 1 - arch/arm64/include/asm/processor.h | 1 - arch/avr32/include/asm/processor.h | 1 - arch/blackfin/include/asm/processor.h | 1 - arch/c6x/include/asm/processor.h | 1 - arch/cris/include/asm/processor.h | 1 - arch/frv/include/asm/processor.h | 1 - arch/h8300/include/asm/processor.h | 1 - arch/hexagon/include/asm/pro...

...at 18:03, Chris Lattner wrote: > >> On Jan 14, 2010, at 10:13 PM, David Conrad wrote: >> >>> Other targets that I know of that could potentially benefit from >>> this optimization being global (that have a clz and bitreverse >>> instruction but not ctz) are AVR32 and C64x, neither of which llvm >>> has backends for yet. >> >> When/if another target wants this, we could add a ISD::RBIT >> operation, >> it doesn't need to be added at the llvm ir level, > > The XCore also has ctlz and bitreverse instructions and not...