search for: armv6t2

Hi, On ARMv6T2 this turns cttz into rbit, clz instead of the 4 instruction sequence it is now. I'm not sure if adding RBIT to ARMISD and doing this optimization in the legalize pass is the best option, but the only better way I could think of doing it was to add a bitreverse intrinsic to llvm ir, which itsel...

...is to say it's associated with -m64, not -mcpu=v9 (although unsurprisingly -m64 does require a V9 or later CPU). I may be wrong, but I think the only distinction in ARM is between arm and thumb code, which do have distinct archtypes in Triple.h I mean for arm we have arm vs armv4, armv5, armv6, armv6t2, armv7-*. Same for thumb - thumb vs thumb2. -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University

On Fri, Jan 15, 2010 at 6:03 PM, Chris Lattner <clattner at apple.com> wrote: > > On Jan 14, 2010, at 10:13 PM, David Conrad wrote: > >> Hi, >> >> On ARMv6T2 this turns cttz into rbit, clz instead of the 4 >> instruction sequence it is now. >> >> I'm not sure if adding RBIT to ARMISD and doing this optimization in >> the legalize pass is the best option, but the only better way I >> could think of doing it was to add a...

On 03/02/2010, at 10:16 PM, Anton Korobeynikov wrote: > Hello, Nathan > >> I've put together some preliminary patches to add frontend support for the sparcv9-* subtarget (ie 64-bit SPARC), modelled on the corresponding x86-64 code - do these look reasonable for inclusion? This doesn't address the codegen side of things yet (isel falls over when trying to actually emit

On Jan 14, 2010, at 10:13 PM, David Conrad wrote: > Hi, > > On ARMv6T2 this turns cttz into rbit, clz instead of the 4 > instruction sequence it is now. > > I'm not sure if adding RBIT to ARMISD and doing this optimization in > the legalize pass is the best option, but the only better way I > could think of doing it was to add a bitreverse int...

...dynamic linker. I would be happy if you could commit it to the SVN. Thanks very much for working on this. It looks like a good starting-point, but there are a couple of issues with the patch at the moment. First, it only handles RelValue up to 22 bits (depending on how you count) in size. But on ARMv6T2 onwards the J1 and J2 fields of the instruction form part of the immediate. Technically, I think a linker is allowed to do what you've done so it's probably good enough for now as long as we put an assertion into the code that RelType isn't too big. Second, I don't think it handles...

Hello, here is a patch to add Thumb call relocation to the dynamic linker. I would be happy if you could commit it to the SVN. Thank you, Jonas -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130524/069287d6/attachment.html> -------------- next part -------------- A non-text attachment was scrubbed...

...ction set that provides a subset of the ARM instruction set and was intended to provide the amount of functionality that compilers required and no more, to reduce codesize in compiled images. What was "thumb" became referred to as "thumb1" after "thumb2" was released (armv6t2), which added features such as condition execution (the IT, "if-then-else" instruction). The ARM architecture is numbered sequentially by evolution, so Thumb is available in v4t (meaning "v4 with Thumb extension") and Thumb-2 is available in v6t2. v7 includes Thumb-2 by defaul...

...et of the ARM > instruction set and was intended to provide the amount of functionality > that compilers required and no more, to reduce codesize in compiled > images. > > What was "thumb" became referred to as "thumb1" after "thumb2" was > released (armv6t2), which added features such as condition execution > (the IT, "if-then-else" instruction). > > The ARM architecture is numbered sequentially by evolution, so Thumb is > available in v4t (meaning "v4 with Thumb extension") and Thumb-2 is > available in v6t2. >...

Hi James, Thanks for the answer, can you elaborate on difference between thumb, thumb2, ARM, thumbv7. I'm a bit lost right now. When specifying thumbv7 llc will generate thumb only code, not thumb2 ? Best Regards Seb > -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] > On Behalf Of James Molloy > Sent: Tuesday, May 29,

Hi, What would be the proper syntax in a C file, using inline assembly, to load a immediate value into an ARM register using clang & integrated assembler? The following syntax is rejected by LLVM: // clang -target armv7em-none-eabi -mthumb #define CONSTANT 0x1234 void __attribute__((naked)) foo(void) { asm volatile ( "ldr r0, =%0 \n"

Hi, peter green wrote: > On 18/05/16 04:50, Tim Northover wrote: > If you don't need/want the various Sanitizer runtimes (e.g. you don't > support sanitizers or already have versions provided with GCC) then > it's as easy as not downloading compiler-rt or removing it from the > projects/ directory before running CMake. The build should carry on > quite happily