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Well this has had me stumped for days now. For months I've been using tinc in TCPOnly because I always received the unknown host error when using UDP. On Monday, i set the flag IndirectData = yes in my host files, and removed the TCPOnly line. Initially, everything worked great. My throughput increased from 600KB/sec to 2MB/sec between the sites. However, I also did some testing with

...c sources of information regarding power analysis in hierarchical models would be gladly received. Thank you Tom. ------------------------------------------------------------------------- Tom Wilding, MSc, PhD, Dip. Stat. Scottish Association for Marine Science, Scottish Marine Institute, OBAN Argyll. PA37 1QA United Kingdom. Phone (+44) (0) 1631 559214 Fax (+44) (0) 1631 559001 ------------------------------------------------------------------------ +++++++++++++++++++++++++++++++ The Scottish Association for Marine Science (SAMS) is registered in Scotland as a Company Limited by Guarantee (S...

...d by Guarantee (SC009292) and is a registered charity (9206). SAMS has an actively trading wholly owned subsidiary company: SAMS Research Services Ltd a Limited Company (SC224404). All Companies in the group are registered in Scotland and share a registered office at Scottish Marine Institute, Oban Argyll PA37 1QA. The content of this message may contain personal views which are not the views of SAMS unless specifically stated. Please note that all email traffic is monitored for purposes of security and spam filtering. As such individual emails may be examined in more detail. [[alternative HTML ve...

Hi All, I have a question about TableGen RegisterClass definition. I need to map different size of MVTs into a register class as below. def TestReg : RegisterClass<"Test", [v8i32, v4i32], ...> When I look at TableGen and CodeGen, it looks the types are used as following: 1. MCRegisterClass's RegSize and Alignment 2. SpillSize in TableGen 3. Type constraint for instruction

Hi, I noticed that a while ago the isSSA flag was removed from MIR, and this property is now computed. However, the deduction only checks the virtual registers (whether they are assigned to more than once). Now I have MIR tests which live after RA, so they only contain physical registers, so the parser determines they are in SSA form. These tests now fail because some of our passes can be

Hi, I found that prologue_end markers where badly placed in my test, and applied https://reviews.llvm.org/D41762 in the hope that it would fix it (I'm on 4.0.1). However, this fix doesn't work for VLIW architectures. At this point we're iterating over bundles, not MachineInstructions, and the FrameSetup flag is set on MachineInstructions, not bundles. If bundling happens in the

Hi, anyone know anything about copy propagation? Matthias, I see this was your code originally? Was there some assumptions you made? I'm hitting an assertion in MachineCopyPropagation::isNopCopy: if (Src == PreviousSrc) { assert(Def == PreviousDef); return true; } This code compares two COPY instruction to see whether they are effectively "the same". The assert assumes

...d by Guarantee (SC009292) and is a registered charity (9206). SAMS has an actively trading wholly owned subsidiary company: SAMS Research Services Ltd a Limited Company (SC224404). All Companies in the group are registered in Scotland and share a registered office at Scottish Marine Institute, Oban Argyll PA37 1QA. The content of this message may contain personal views which are not the views of SAMS unless specifically stated. Please note that all email traffic is monitored for purposes of security and spam filtering. As such individual emails may be examined in more detail. [[alternative HTML ve...

...d by Guarantee (SC009292) and is a registered charity (9206). SAMS has an actively trading wholly owned subsidiary company: SAMS Research Services Ltd a Limited Company (SC224404). All Companies in the group are registered in Scotland and share a registered office at Scottish Marine Institute, Oban Argyll PA37 1QA. The content of this message may contain personal views which are not the views of SAMS unless specifically stated. Please note that all email traffic is monitored for purposes of security and spam filtering. As such individual emails may be examined in more detail. -------------- next par...

...d by Guarantee (SC009292) and is a registered charity (9206). SAMS has an actively trading wholly owned subsidiary company: SAMS Research Services Ltd a Limited Company (SC224404). All Companies in the group are registered in Scotland and share a registered office at Scottish Marine Institute, Oban Argyll PA37 1QA. The content of this message may contain personal views which are not the views of SAMS unless specifically stated. Please note that all email traffic is monitored for purposes of security and spam filtering. As such individual emails may be examined in more detail. [[alternative HTML ve...

Hello everyone, Consider we have this following set of code: int foo() { int a,b; a = __builtin_XX(0x11); b = __builtin_XX(0x11); return a+b; } The problem currently is that LLVM eliminated the second call and copied the result from the first call into a new set of registers. Is there is a way to force LLVM to generate two explicit calls to a builtin function. The builtin takes in an integer

...d by Guarantee (SC009292) and is a registered charity (9206). SAMS has an actively trading wholly owned subsidiary company: SAMS Research Services Ltd a Limited Company (SC224404). All Companies in the group are registered in Scotland and share a registered office at Scottish Marine Institute, Oban Argyll PA37 1QA. The content of this message may contain personal views which are not the views of SAMS unless specifically stated. Please note that all email traffic is monitored for purposes of security and spam filtering. As such individual emails may be examined in more detail. [[alternative HTML ve...

Hi folks, Not sure if this is the right mailing list target, but I'm trying out the new LLVM 7.0 packages found at http://apt.llvm.org by porting over an existing LLVM 6.0 project of ours to the new version. In doing so, I found that the executable always segfaulted at the same spot with no explanation: 0x0000000000fefe33 in

Hello, our web consulting firm is looking for Rails developers located in/around Los Angeles. Please check out our website and send me your resume if you are interested. Both FT and contractors! Thanks for your consideration. Regards, JP -- James E Payne principal rhombus technologies, inc. 1606 argyle ave, los angeles, ca 90028 t 310.651.6187 m 310.721.6838 www.rhombus-technologies.com

Hi Everyone, Just a friendly announcement for yet-another Rails project gone live, highnote. The concept is simple - you upload your iTunes XML Library and highnote will automatically keep an eye on upcoming concerts and notify you about them. Sort of a "set it and forget it" for shows. No more browsing around the troubadour website and various places ... highnote knows what you like

Hi list, I happened to read below thread (written in 3 years ago). I think I may need this ReadAdvance feature to work with my ARCH. It is about the scheduler info which describes reading my ARCH's vector register. There are different latencies since forwarding/bypass appears. I give it as below example: def : WriteRes<WriteVector, [MyArchVALU]> { let Latency = 6; } ... def

I want to configure a server with Samba. I made some test with Mandriva 2006 but I'm not sure it's the best linux performance ! What do you think ? Did you make some test between different linux version ? Best Regards, Luc Sainte-Marie Network Administrator

...d by Guarantee (SC009292) and is a registered charity (9206). SAMS has an actively trading wholly owned subsidiary company: SAMS Research Services Ltd a Limited Company (SC224404). All Companies in the group are registered in Scotland and share a registered office at Scottish Marine Institute, Oban Argyll PA37 1QA. The content of this message may contain personal views which are not the views of SAMS unless specifically stated. Please note that all email traffic is monitored for purposes of security and spam filtering. As such individual emails may be examined in more detail. [[alternative HTML ve...

Hi, I think there might be a bug in the tail duplicator (called from MachineBlockPlacement in my case), when duplicating a block that contains an implicit fall-through. Suppose you have the following blocks BB#1: Predecessors according to CFG: BB#2 ... conditional_branch <BB#3> < implicit fall-through to BB#2 > Successors according to CFG: BB#2 BB#3 BB#2:

I actually sent this to Guus directly before realizing I could send it to this mailing list. So, Sorry about that Guus!! I'm trying to connect two remote networks together with Tinc. I have Tinc installed on a host (host name is "donald") at location A, and Tinc installed on a host (host name is "irfan") at location B. Right now, donald and irfan can talk to eachother.