search for: antidep_all

...ith this some today for my PPC 440 chips. These are embedded chips (multiple pipelines but in-order), and may be more similar to your ARMs than to the PPC-970 style designs... I was able to get reasonable PPC 440 code generation by using the ILP scheduler pre-RA and then the post-RA scheduler with ANTIDEP_ALL (and my load/store reordering patch). This worked significantly better than using either hybrid or ilp alone (with or without setting HasReadyFilter). I was looking at my primary use case which is partially-unrolled loops with loads, stores and floating-point calculations. This seems to work b/c I...

...y PPC 440 chips. These are > embedded chips (multiple pipelines but in-order), and may be more > similar to your ARMs than to the PPC-970 style designs... > > I was able to get reasonable PPC 440 code generation by using the ILP > scheduler pre-RA and then the post-RA scheduler with ANTIDEP_ALL (and my > load/store reordering patch). This worked significantly better than > using either hybrid or ilp alone (with or without setting > HasReadyFilter). I was looking at my primary use case which is > partially-unrolled loops with loads, stores and floating-point > calculations....

On Dec 19, 2011, at 6:51 AM, Hal Finkel <hfinkel at anl.gov> wrote: > On Tue, 2011-10-25 at 21:00 -0700, Andrew Trick wrote: > Now, to generate the best PPC schedules, there is one thing you may >> want to override. The scheduler's priority function has a >> HasReadyFilter attribute (enum). It can be overriden by specializing >> hybrid_ls_rr_sort. Setting this to

On Tue, 2011-10-25 at 21:00 -0700, Andrew Trick wrote: Now, to generate the best PPC schedules, there is one thing you may > want to override. The scheduler's priority function has a > HasReadyFilter attribute (enum). It can be overriden by specializing > hybrid_ls_rr_sort. Setting this to "true" enables proper ILP > scheduling, and maximizes the instructions that can

----- Original Message ----- > > > > hi, > I have few question about breaking anti-dependence of postRAScheduler > in LLVM. > when I use command line "clang -target arm -mcpu=cortex-a8 -O2 > -integrated-as -c test.c -o test.o" > and get objdump file as follows: > ldr r1, [r0,#16]----(1 > str r1, [r0,#32]----(2 > ldr r1, [r0,#12]----(3 > str r1,

hi, I have few question about breaking anti-dependence of postRAScheduler in LLVM. when I use command line "clang -target arm -mcpu=cortex-a8 -O2 -integrated-as -c test.c -o test.o" and get objdump file as follows: ldrr1, [r0,#16]----(1 str r1, [r0,#32]----(2 ldr r1, [r0,#12]----(3 str r1, [r0,#36]----(4 ldr r1, [r0,#08]----(5 str r1, [r0,#40]----(6 However, I expect that instruction

...e > > embedded chips (multiple pipelines but in-order), and may be more > > similar to your ARMs than to the PPC-970 style designs... > > > > I was able to get reasonable PPC 440 code generation by using the ILP > > scheduler pre-RA and then the post-RA scheduler with ANTIDEP_ALL (and my > > load/store reordering patch). This worked significantly better than > > using either hybrid or ilp alone (with or without setting > > HasReadyFilter). I was looking at my primary use case which is > > partially-unrolled loops with loads, stores and floating-point...