Displaying 6 results from an estimated 6 matches for "an40_0_7".
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an32_0_7
2012 Jan 05
0
[LLVMdev] Spilling of partly (un)defined registers
...nction accumconv:
Function Live Ins: %a0_gh in %vreg0, %a1_gh in %vreg1
BB#0: derived from LLVM BB %0
Live Ins: %a0_gh %a1_gh
%vreg1<def> = COPY %a1_gh; aNgh_0_7:%vreg1
[...]
%vreg56<def> = mv_any16 0; aNl_0_7:%vreg56
%vreg57<def> = REG_SEQUENCE %vreg1, hi24, %vreg56, lo16;
aN40_0_7:%vreg57 aNgh_0_7:%vreg1 aNl_0_7:%vreg56
So the in-argument in a1_gh is saved in vreg1, and used later in a
REG_SEQUENCE instruction to write a full register, vreg57.
After the REG_SEQUENCE has been eliminated we instead get
16 %vreg57:hi24<def> = COPY %a1_gh<kill>; aN40_0_7:%vreg57...
2012 Jan 19
4
[LLVMdev] Problem with cross class joins in the RegisterCoalescer
...ll instructions where it is now used.
For example, by joining %vreg4, %vreg7 and %vreg9 the following code
%vreg7<def> = COPY %vreg4:lo16; aNl_0_7:%vreg7 aN32_0_7:%vreg4
%vreg9<def> = COPY %vreg7; rN:%vreg9 aNl_0_7:%vreg7
%vreg17<def> = load %vreg9<kill>; aN40_0_7:%vreg17 rN:%vreg9
is turned into
%vreg17<def> = load %vreg4:lo16<kill>; aN40_0_7:%vreg17
aN32_0_7:%vreg4
The load instruction however, can only use registers from the rN class,
but the coalescer has changed so it now uses the lo16 part of a aN32
register (which it cannot).
Mo...
2012 Jan 19
0
[LLVMdev] Problem with cross class joins in the RegisterCoalescer
...now used.
>
> For example, by joining %vreg4, %vreg7 and %vreg9 the following code
>
> %vreg7<def> = COPY %vreg4:lo16; aNl_0_7:%vreg7 aN32_0_7:%vreg4
> %vreg9<def> = COPY %vreg7; rN:%vreg9 aNl_0_7:%vreg7
> %vreg17<def> = load %vreg9<kill>; aN40_0_7:%vreg17 rN:%vreg9
>
> is turned into
>
> %vreg17<def> = load %vreg4:lo16<kill>; aN40_0_7:%vreg17
> aN32_0_7:%vreg4
>
> The load instruction however, can only use registers from the rN class,
> but the coalescer has changed so it now uses the lo16 part of...
2012 Jan 20
1
[LLVMdev] Problem with cross class joins in the RegisterCoalescer
...now used.
>
> For example, by joining %vreg4, %vreg7 and %vreg9 the following code
>
> %vreg7<def> = COPY %vreg4:lo16; aNl_0_7:%vreg7 aN32_0_7:%vreg4
> %vreg9<def> = COPY %vreg7; rN:%vreg9 aNl_0_7:%vreg7
> %vreg17<def> = load %vreg9<kill>; aN40_0_7:%vreg17 rN:%vreg9
>
> is turned into
>
> %vreg17<def> = load %vreg4:lo16<kill>; aN40_0_7:%vreg17
> aN32_0_7:%vreg4
>
> The load instruction however, can only use registers from the rN class,
> but the coalescer has changed so it now uses the lo16 part of...
2014 Aug 22
2
[LLVMdev] Help with definition of subregisters; spill, rematerialization and implicit uses
...uentin,
On 08/19/14 18:58, Quentin Colombet wrote:
[...]
> It seems that you will have to debug further the *** Bad machine code: Instruction loads from dead spill slot *** before we can be of any help.
Yes, I've done some more digging. Sorry for the long mail...
I get:
Inline spilling aN40_0_7:%vreg1954 [5000r,5056r:0)[5056r,5348r:1)
0 at 5000r 1 at 5056r
At this point I have the following live ranges for vreg1954:
%vreg1954 [5000r,5056r:0)[5056r,5348r:1) 0 at 5000r 1 at 5056r
And vreg1954 is mentioned in these instructions:
5000B %vreg1954:hi16<def,read-undef> = mv_any1...
2014 Aug 19
2
[LLVMdev] Help with definition of subregisters; spill, rematerialization and implicit uses
Hi Quentin,
On 08/15/14 19:01, Quentin Colombet wrote:
[...]
>> The question is: How should true subregister definitions be
>> expressed so that they do not interfere with each other? See the
>> detailed problem description below.
>
> We do have a limitation in our current liveness tracking for
> sub-register. Therefore, I am not sure that is possible.
>
>