Displaying 7 results from an estimated 7 matches for "an32_0_7".
2011 Nov 18
1
[LLVMdev] Greedy regalloc
...d cleared, as another spill of same value is inserted. The former spill is however not NOP:ed, but KILL:ed, thus the operands get a kill status. The code becomes:
%vreg301<def> = mv32Imm 200000000, pred:0, pred:%noreg, %CCReg<imp-def,dead>, %ac0<imp-use>, %ac1<imp-use>; aN32_0_7:%vreg301
Store32FI %vreg301, <fi#93>, pred:0, pred:%noreg, %CCReg<imp-def>; mem:ST4[FixedStack93] aN32_0_7:%vreg301
KILL %vreg301, <fi#93>, 0, %noreg, %CCReg<imp-def>; mem:ST4[FixedStack93] aN32_0_7:%vreg301
%a0_32<def> = COPY %vreg301; aN32_0_7:%vreg301
T...
2012 Jan 19
4
[LLVMdev] Problem with cross class joins in the RegisterCoalescer
...oss class joins are carried out that makes
the code turn out illegal, because the "new" register class is not
allowed in all instructions where it is now used.
For example, by joining %vreg4, %vreg7 and %vreg9 the following code
%vreg7<def> = COPY %vreg4:lo16; aNl_0_7:%vreg7 aN32_0_7:%vreg4
%vreg9<def> = COPY %vreg7; rN:%vreg9 aNl_0_7:%vreg7
%vreg17<def> = load %vreg9<kill>; aN40_0_7:%vreg17 rN:%vreg9
is turned into
%vreg17<def> = load %vreg4:lo16<kill>; aN40_0_7:%vreg17
aN32_0_7:%vreg4
The load instruction however, can only u...
2012 Jan 19
0
[LLVMdev] Problem with cross class joins in the RegisterCoalescer
...ut that makes
> the code turn out illegal, because the "new" register class is not
> allowed in all instructions where it is now used.
>
> For example, by joining %vreg4, %vreg7 and %vreg9 the following code
>
> %vreg7<def> = COPY %vreg4:lo16; aNl_0_7:%vreg7 aN32_0_7:%vreg4
> %vreg9<def> = COPY %vreg7; rN:%vreg9 aNl_0_7:%vreg7
> %vreg17<def> = load %vreg9<kill>; aN40_0_7:%vreg17 rN:%vreg9
>
> is turned into
>
> %vreg17<def> = load %vreg4:lo16<kill>; aN40_0_7:%vreg17
> aN32_0_7:%vreg4
>
>...
2012 Jan 20
1
[LLVMdev] Problem with cross class joins in the RegisterCoalescer
...ut that makes
> the code turn out illegal, because the "new" register class is not
> allowed in all instructions where it is now used.
>
> For example, by joining %vreg4, %vreg7 and %vreg9 the following code
>
> %vreg7<def> = COPY %vreg4:lo16; aNl_0_7:%vreg7 aN32_0_7:%vreg4
> %vreg9<def> = COPY %vreg7; rN:%vreg9 aNl_0_7:%vreg7
> %vreg17<def> = load %vreg9<kill>; aN40_0_7:%vreg17 rN:%vreg9
>
> is turned into
>
> %vreg17<def> = load %vreg4:lo16<kill>; aN40_0_7:%vreg17
> aN32_0_7:%vreg4
>
>...
2016 Mar 04
2
PHI node to different register class vs TailDuplication
...vreg12
brr_uncond <BB#4>;
Successors according to CFG: BB#4(?%)
BB#4: derived from LLVM BB %bb4
Predecessors according to CFG: BB#2 BB#3
%vreg2<def> = PHI %vreg0, <BB#2>, %vreg1, <BB#3>; rN:%vreg2
aNlh_0_7:%vreg0 aNlh_rN:%vreg1
mv_a32_r16_rmod1 %vreg3, %vreg2; aN32_0_7:%vreg3 rN:%vreg2
brr_uncond <BB#6>;
Successors according to CFG: BB#6(?%)
Then TailDuplication runs
Tail-duplicating into PredBB: BB#2: derived from LLVM BB %bb2
[...]
From Succ: BB#4: derived from LLVM BB %bb4
and we get:
BB#2: derived from LLVM BB %bb2
Predecessors accordin...
2019 Sep 02
2
virtual subregister liveness?
...> don’t care about the contain of the other lane.)
>
> Could you provide the MIR before and after dead-mi-elimination? Just
> the part where %5 is involved should suffice.
Thanks. So this is what it looks like before register coalescing (bb.3
dominates bb.1):
bb.1:
...
%22:an32_0_7 = COPY killed %5.hiPair_then_loAcc
...
bb.3:
...
%5:an32quads = COPY killed %13
%5.hiPair_then_hiAcc:an32quads = COPY undef %11
...
After register coalescing and until dead-mi-elimination, it looks like
this:
bb.0:
...
undef %5.hiPair_then_loAcc:an32quads = COPY...
2019 Aug 30
2
virtual subregister liveness?
Hi,
After dead-mi-elimination I'm experiencing a machine verifier failure
at this virtual subregister write:
%5.sub1 = COPY undef %11
The machine verifier essentially complains that the rest of the
register is undefined (a subregister write implies a "read" of the
other parts).
So the problem is that dead-mi-elimination has removed the previously
existing defines of %5.sub0.