search for: amd_iommu_unmap_page

...n", gfn); spin_unlock_irqrestore(&hd->mapping_lock, flags); + amd_iov_error("Invalid IO pagetable entry gfn = %lx\n", gfn); return -EFAULT; } set_iommu_l1e_present(iommu_l2e, gfn, (u64)mfn << PAGE_SHIFT, iw, ir); @@ -493,8 +493,8 @@ int amd_iommu_unmap_page(struct domain * if ( iommu_l2e == 0 ) { - amd_iov_error("Invalid IO pagetable entry gfn = %lx\n", gfn); spin_unlock_irqrestore(&hd->mapping_lock, flags); + amd_iov_error("Invalid IO pagetable entry gfn = %lx\n", gfn); return -EF...

This patch set adds basic supports for amd next generation iommu (IOMMUv2) hardware. IOMMUv2 supports various new features advertised by iommu extended feature register. It introduces guest level IO translation and supports state-of-the-art ATS/ATC devices with demand paging capability. Please refer to AMD IOMMU Architectural Specification [1] for more details. Thanks, Wei [1]