search for: amd_iommu_map_page

...amd/pci_amd_iommu.c +++ b/xen/drivers/passthrough/amd/pci_amd_iommu.c @@ -230,8 +230,16 @@ static void __init amd_iommu_dom0_init(s if ( !iommu_passthrough && !need_iommu(d) ) { /* Set up 1:1 page table for dom0 */ - for ( i = 0; i < max_page; i++ ) - amd_iommu_map_page(d, i, i, IOMMUF_readable|IOMMUF_writable); + for ( i = 0; i < max_pdx; i++ ) + { + unsigned long pfn = pdx_to_pfn(i); + + /* + * XXX Should we really map all non-RAM (above 4G)? Minimally + * a pfn_valid() check would seem desirable her...

Signed-off-by: Jan Beulich <jbeulich@novell.com> --- 2009-01-27.orig/xen/drivers/passthrough/amd/iommu_map.c 2009-01-30 08:43:35.000000000 +0100 +++ 2009-01-27/xen/drivers/passthrough/amd/iommu_map.c 2009-01-30 08:46:29.000000000 +0100 @@ -461,8 +461,8 @@ int amd_iommu_map_page(struct domain *d, iommu_l2e = iommu_l2e_from_pfn(hd->root_table, hd->paging_mode, gfn); if ( iommu_l2e == 0 ) { - amd_iov_error("Invalid IO pagetable entry gfn = %lx\n", gfn); spin_unlock_irqrestore(&hd->mapping_lock, flags); + amd_iov_er...

This patch set adds basic supports for amd next generation iommu (IOMMUv2) hardware. IOMMUv2 supports various new features advertised by iommu extended feature register. It introduces guest level IO translation and supports state-of-the-art ATS/ATC devices with demand paging capability. Please refer to AMD IOMMU Architectural Specification [1] for more details. Thanks, Wei [1]