Displaying 5 results from an estimated 5 matches for "alu_rr".
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alu1_rr
2016 Jan 28
2
Specifying DAG patterns in the instruction
I'm confused about how to specify DAG patterns for a given instruction
Here is an example for my target
class ALU1_RR<bits<4> subOp, string asmstr, SDNode OpNode>
: ALU_RR<subOp, asmstr,
[(set GPR:$rD, (OpNode (i32 GPR:$rA), (i32 GPR:$rB)))]>;
def ADD : ALU1_RR<0x0, "l.add", add>;
The set operation simply creates a list. The add operation creates a union.
So at the end [(set GPR:$rD, (OpNode (i32 GPR:$rA), (i32 GPR:$rB)))]
becomes...
2020 May 12
2
BPF tablegen+codegen question
In BPF, an ADD instruction is defined as a 2 register instruction:
0x0f. add dst, src. dst += src
In BPFInstrInfo.td this kind of ALU instruction is defined with:
def _rr : ALU_RR<BPF_ALU64, Opc,
(outs GPR:$dst),
(ins GPR:$src2, GPR:$src),
"$dst "#OpcodeStr#" $src",
[(set GPR:$dst, (OpNode i64:$src2, i64:$src))]>;
How does tablegen+codegen ensure that dst and src2 are the s...
2016 Jan 29
2
Specifying DAG patterns in the instruction
...llvm-dev <
> llvm-dev at lists.llvm.org> wrote:
>
>> I'm confused about how to specify DAG patterns for a given instruction
>>
>> Here is an example for my target
>>
>> class ALU1_RR<bits<4> subOp, string asmstr, SDNode OpNode>
>> : ALU_RR<subOp, asmstr,
>> [(set GPR:$rD, (OpNode (i32 GPR:$rA), (i32 GPR:$rB)))]>;
>>
>> def ADD : ALU1_RR<0x0, "l.add", add>;
>>
>> The set operation simply creates a list. The add operation creates a
>> union. So at the end [(set GPR:...
2016 Jan 29
0
Specifying DAG patterns in the instruction
...at lists.llvm.org> wrote:
>>
>>> I'm confused about how to specify DAG patterns for a given instruction
>>>
>>> Here is an example for my target
>>>
>>> class ALU1_RR<bits<4> subOp, string asmstr, SDNode OpNode>
>>> : ALU_RR<subOp, asmstr,
>>> [(set GPR:$rD, (OpNode (i32 GPR:$rA), (i32 GPR:$rB)))]>;
>>>
>>> def ADD : ALU1_RR<0x0, "l.add", add>;
>>>
>>> The set operation simply creates a list. The add operation creates a
>>> union. S...
2016 Jan 31
2
Specifying DAG patterns in the instruction
...:
>>>
>>>> I'm confused about how to specify DAG patterns for a given instruction
>>>>
>>>> Here is an example for my target
>>>>
>>>> class ALU1_RR<bits<4> subOp, string asmstr, SDNode OpNode>
>>>> : ALU_RR<subOp, asmstr,
>>>> [(set GPR:$rD, (OpNode (i32 GPR:$rA), (i32 GPR:$rB)))]>;
>>>>
>>>> def ADD : ALU1_RR<0x0, "l.add", add>;
>>>>
>>>> The set operation simply creates a list. The add operation creates a
&...