Displaying 4 results from an estimated 4 matches for "alu1_rr".
2016 Jan 28
2
Specifying DAG patterns in the instruction
I'm confused about how to specify DAG patterns for a given instruction
Here is an example for my target
class ALU1_RR<bits<4> subOp, string asmstr, SDNode OpNode>
: ALU_RR<subOp, asmstr,
[(set GPR:$rD, (OpNode (i32 GPR:$rA), (i32 GPR:$rB)))]>;
def ADD : ALU1_RR<0x0, "l.add", add>;
The set operation simply creates a list. The add operation creates a union.
So at the...
2016 Jan 29
2
Specifying DAG patterns in the instruction
...etSelectionDAG.td?
> On Thu, Jan 28, 2016 at 7:33 PM, Rail Shafigulin via llvm-dev <
> llvm-dev at lists.llvm.org> wrote:
>
>> I'm confused about how to specify DAG patterns for a given instruction
>>
>> Here is an example for my target
>>
>> class ALU1_RR<bits<4> subOp, string asmstr, SDNode OpNode>
>> : ALU_RR<subOp, asmstr,
>> [(set GPR:$rD, (OpNode (i32 GPR:$rA), (i32 GPR:$rB)))]>;
>>
>> def ADD : ALU1_RR<0x0, "l.add", add>;
>>
>> The set operation simply creates...
2016 Jan 29
0
Specifying DAG patterns in the instruction
...Thu, Jan 28, 2016 at 7:33 PM, Rail Shafigulin via llvm-dev <
>> llvm-dev at lists.llvm.org> wrote:
>>
>>> I'm confused about how to specify DAG patterns for a given instruction
>>>
>>> Here is an example for my target
>>>
>>> class ALU1_RR<bits<4> subOp, string asmstr, SDNode OpNode>
>>> : ALU_RR<subOp, asmstr,
>>> [(set GPR:$rD, (OpNode (i32 GPR:$rA), (i32 GPR:$rB)))]>;
>>>
>>> def ADD : ALU1_RR<0x0, "l.add", add>;
>>>
>>> The set o...
2016 Jan 31
2
Specifying DAG patterns in the instruction
...M, Rail Shafigulin via llvm-dev <
>>> llvm-dev at lists.llvm.org> wrote:
>>>
>>>> I'm confused about how to specify DAG patterns for a given instruction
>>>>
>>>> Here is an example for my target
>>>>
>>>> class ALU1_RR<bits<4> subOp, string asmstr, SDNode OpNode>
>>>> : ALU_RR<subOp, asmstr,
>>>> [(set GPR:$rD, (OpNode (i32 GPR:$rA), (i32 GPR:$rB)))]>;
>>>>
>>>> def ADD : ALU1_RR<0x0, "l.add", add>;
>>>>
&g...