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...projects using autoconf. Those patches are originally written for the buildroot project, and you can browse them anytime on the project repository [0]. Until a release come out that render them useless of course. Best Regards, Ben. [0] https://git.busybox.net/buildroot/tree/boot/syslinux Beno?t Allard (4): memdisk: Force ld output format to 32-bits utils: Use the host toolchain to build. lzo: Use the host toolchain for prepcore efi/wrapper: build it with the host toolchain. efi/Makefile | 2 +- lzo/Makefile | 7 +++++-- memdisk/Makefile | 2 +- utils/Makefile | 12 ++++++--...

Signed-off-by: Beno?t Allard <benoit.allard at greenbone.net> --- efi/fio.h | 9 --------- 1 file changed, 9 deletions(-) diff --git a/efi/fio.h b/efi/fio.h index 65fff8d..a1bfe68 100644 --- a/efi/fio.h +++ b/efi/fio.h @@ -11,15 +11,6 @@ #define MAX_EFI_ARGS 64 #define WS(c16) (c16 == L' ' || c16 ==...

...ch [1] I required, but that one isn't authored by me. I would be grateful if you integrate it in your next release as well. Best Regards, Ben. [0] https://buildroot.org [1] https://bugs.debian.org/cgi-bin/bugreport.cgi?att=1;bug=846679;filename=syslinux_6.03%2Bdfsg-14.1.debdiff;msg=10 Beno?t Allard (2): memdisk: Force ld output format to 32-bits utils: Use the host toolchain to build. memdisk/Makefile | 2 +- utils/Makefile | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) -- 2.1.4

Hi all, The IndVarSimplify pass seems to be too aggressive when it enlarge the induction variable type ; this can pessimize the generated code when the new induction variable size is not natively supported by the target. This is probably not an issue for x86_64, which supports natively all types, but it is a real one for several embedded targets, with very few native types. I attached a patch to

On 04/14/2014 02:31 PM, Arnaud Allard de Grandmaison wrote: > Hi All, > > As kindly pointed by Sebastian, please forget my point about the release > script. I read the mail from Tom 2 days ago, and forgot that the script was > available in the tag / branch when I acted today :( > > I uploaded clang+llvm-3.4.1-rc1-...

...ut to a different area, as everything is taking place in the same BB. Is this some known issue ? I could not find a bug report matching this. -- Arnaud de Grandmaison -----Original Message----- From: Eli Friedman [mailto:eli.friedman at gmail.com] Sent: Sunday, March 13, 2011 11:08 PM To: Arnaud Allard de Grandmaison Cc: llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] IndVarSimplify too aggressive ? On Sun, Mar 13, 2011 at 5:01 PM, Arnaud Allard de Grandmaison <Arnaud.AllardDeGrandMaison at dibcom.com> wrote: > Hi all, > > The IndVarSimplify pass seems to be too aggressive when it e...

...anted to give a try to the pbqp :) I will add the hook to the pbqp and propose a patch if this looks clean enough. Thanks, -- Arnaud de Grandmaison -----Original Message----- From: Jakob Stoklund Olesen [mailto:stoklund at 2pi.dk] Sent: Monday, June 06, 2011 9:28 PM To: Peter Lawrence Cc: Arnaud Allard de Grandmaison; llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] PBQP & register pairing On Jun 6, 2011, at 12:14 PM, Peter Lawrence wrote: > Arnaud, > another way to look at it, if the description of your register sets includes "pairs", > is that your assembly...

Hi Arnaud, That sounds great. I look forward to seeing a patch. You may also look forward to big performance improvements in the PBQP allocator: I'm working on updates which will improve compile speeds and massively reduce memory use. Regards, Lang. On Tue, Jun 7, 2011 at 7:02 PM, Arnaud Allard de Grandmaison < Arnaud.AllardDeGrandMaison at dibcom.com> wrote: > > I also considered this approach, but did not want to dive in the constraint > handling for now. > > The PBQP path seemed easier at first sight --- and was easy to setup. And I > always wanted to give a tr...

On Tue, Oct 19, 2010 at 12:19 AM, Arnaud Allard de Grandmaison <Arnaud.AllardDeGrandMaison at dibcom.com> wrote: >> But if the usage was in a loop it would be better (at the cost of >> register pressure) to materialise 5 into a register outside of the >> loop and use the register repeatedly in the loop. > > Bouncing...

Committed at r194269 Thanks Jakob ! Cheers, -- Arnaud On Fri, Nov 8, 2013 at 6:34 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk>wrote: > > On Nov 8, 2013, at 7:40 AM, Arnaud Allard de Grandmaison < > arnaud.adegm at gmail.com> wrote: > > > Based on discussions with Lang Hames and Jakob Stoklund Olesen at the > hacker's lab, and in the light of upcoming work on the PBQP register > allocator, it was though that CalcSpillWeights does not need to be a...

On Mar 13, 2011, at 2:01 PM, Arnaud Allard de Grandmaison wrote: > Hi all, > > The IndVarSimplify pass seems to be too aggressive when it enlarge the induction variable type ; this can pessimize the generated code when the new induction variable size is not natively supported by the target. This is probably not an issue for x86_6...

On Jun 6, 2011, at 7:07 AM, Arnaud Allard de Grandmaison wrote: > Hi All, > > My target has some instructions requiring register pairs. I decided to give a try to the PBQP allocator : it is working fine in 99% of the cases, but I am stumbling on the following issue. > > Instruction ‘MPQD’ takes 3 register operands input...

Oops. Forgot the mailing list in the reply. -- Arnaud de Grandmaison ________________________________________ From: Arnaud Allard de Grandmaison Sent: Thursday, June 03, 2010 9:57 PM To: Jakob Stoklund Olesen Subject: RE: [LLVMdev] Unused argument registers can not be reused ? I have finally been able to make some progress : the bug has been introduced/revealed by svn commit #95493, which enabled DeadMachineInstructionElimPa...

...rated : constant folding and pure functions handling. Only showing constant folding does not seem very appealing for an optimizer :) Best regards, -- Arnaud de Grandmaison -----Original Message----- From: Dan Gohman [mailto:gohman at apple.com] Sent: Tuesday, November 16, 2010 6:45 PM To: Arnaud Allard de Grandmaison Cc: llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] Optimization of calls to functions without side effects (from Kaleidoscope example) On Nov 16, 2010, at 1:19 AM, Arnaud Allard de Grandmaison wrote: > Hi Dan, > > The tutorial in r119335 does not build : the basicAA pass c...

On Mar 13, 2011, at 2:01 PM, Arnaud Allard de Grandmaison wrote: > Hi all, > > The IndVarSimplify pass seems to be too aggressive when it enlarge the induction variable type ; this can pessimize the generated code when the new induction variable size is not natively supported by the target. This is probably not an issue for x86_6...

While migrating my codebase from llvm-2.6 to llvm-2.7, I found a different behaviour in the register allocation. I have been able to reproduce it using the msp430 backend, with the 2.7 release as well as the svn head. For the msp430, the first four parameters of a function are passed thru registers. What I observe is that if those parameters are not used inside the function, those registers can

On Nov 16, 2010, at 1:19 AM, Arnaud Allard de Grandmaison wrote: > Hi Dan, > > The tutorial in r119335 does not build : the basicAA pass creation needs to be declared. This is addressed with the 'missing-include' patch, which updates both source code & documentation. Applied, thanks. > The second point is that be...

A follow-up question: Is there a way to make different passes accept one command line option that will affect all of them? For example, I'd like to have a -optStrength parameter, that can be given to all of my passes simultaneously. Thanks a lot, Guy Arnaud Allard de Grandmaison wrote: > > Hi Harel, > > Several existing passes can take command line arguments. Have a look at > lib/Transforms/Scalar/LoopUnrollPass.cpp for example. Its command line > arguments are defined using the cl::opt objects. > > Best regards, > -- > Arnau...

Hi All, My target has some instructions requiring register pairs. I decided to give a try to the PBQP allocator : it is working fine in 99% of the cases, but I am stumbling on the following issue. Instruction 'MPQD' takes 3 register operands inputs, with the constraint that operands 0 and 2 must be consecutive registers. Operand 1 has no particular constraint. It has no output register.

Hi Simon, The page will be updated later today with the new rate. Kind regards, Arnaud On Tue, Feb 26, 2019 at 12:52 PM Simon Dardis via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Hi, > > The EventBrite page is showing sales have ended, will it be reopening with > the higher rate soon? > > Thanks, > Simon > > On Tue, 26 Feb 2019 at 00:20, Tanya Lattner via