search for: addw

...I don't think it's quite enough. Options include: 1. Only have one set of register definitions, and have the variable sized register class determine the bit width. The problem is there are often some instructions where I think you need to have registers modelled as subregisters. e.g. SLLW, ADDW etc in 64-bit RISC-V. These operate on 32-bit values and write the results sign-extended to the target 64-bit register. 2. Define both the 64-bit registers and the 32-bit subregisters, but make MatchRegisterName's behaviour change based on the HwMode. This works around the fact there are multi...

Hi, I have a Liebert PowerSure Personal XT that I have connected via its USB interface. lsusb shows that it is there and when I plugged in I got the kernel messages: Jul 3 11:25:37 mint kernel: usb 2-2.2: new low speed USB device using address 4 Jul 3 11:25:38 mint kernel: hiddev96: USB HID v1.11 Device [LIEBERT PowerSure Personal XT] on usb-0000:00:10.0-2.2 The documentation suggests that

I've been playing around with llvm lately and I was wondering something about the bitcode instructions for basic arithmetic. Is there any plan to provide instructions that perform widening multiply, or add with carry? It might be written as: mulw i32 %lhs %rhs -> i64 ; widening multiply addw i32 %lhs %rhs -> i33 ; widening add addc i32 %lhs, i32 %rhs, i1 %c -> i33 ; add with carry Alternatively, would something like following get reduced to a single multiply and two stores on arch's that support wide multiplies, like x86-32 and ARM? define void @mulw(i32* hidest, i32* lodes...

...i32, i32* @c, align 4, !tbaa !1 %add = add nsw i32 %1, %0 store i32 %add, i32* @a, align 4, !tbaa !1 And we'd want to generate ldw %r0, at b ; load b (32 bits) from memory with sign extension to 64 bits ldw %r1, at c ; load c (32 bits) from memory with sign extension to 64 bits addw %r2,%r0,%r1 ; add lower 32 bits of r0 and r1 stw @a,%r2 ; store lower 32 bits of r2 to a If I define the ldw instruction faithfully according to the HW, that is, extending to 64 bits, it won't match the load i32. Does that mean I will need to define both 32 and 64 bit versions (via a mult...

The size suffix thing is a weird quirk in our assembler I should look into fixing. Instructions in at&t syntax usually have a size suffix that is often optional For example: add %ax, %bx and addw %ax, %bx Are equivalent because the register name indicates the size. but for an instruction like this addw $1, (%ax) There is nothing to infer the size from so an explicit suffix is required. So for an instruction like "add %ax, %bx" from above, we try to guess the size suffix from...

...gt; wrote: > > The size suffix thing is a weird quirk in our assembler I should look > into > > fixing. Instructions in at&t syntax usually have a size suffix that is > often > > optional > > > > For example: > > add %ax, %bx > > and > > addw %ax, %bx > > > > Are equivalent because the register name indicates the size. > > > > but for an instruction like this > > addw $1, (%ax) > > > > There is nothing to infer the size from so an explicit suffix is > required. > > > > So for an...

...3, %eax"); DEF_NATIVE(pv_cpu_ops, clts, "clts"); DEF_NATIVE(pv_cpu_ops, read_tsc, "rdtsc"); +DEF_NATIVE(, unlock1, UNLOCK_LOCK_PREFIX + "addb $"__stringify(__TICKET_LOCK_INC)", (%eax)"); +DEF_NATIVE(, unlock2, UNLOCK_LOCK_PREFIX + "addw $"__stringify(__TICKET_LOCK_INC)", (%eax)"); + +extern void __unlock_wrong_size(void) + __compiletime_error("Bad argument size for unlock"); + unsigned paravirt_patch_ident_32(void *insnbuf, unsigned len) { /* arg in %eax, return in %eax */ @@ -24,6 +34,21 @@ unsigned p...

I am looking at one of these, see: http://www.cclonline.com/product-info.asp?product_id=14622&category_id=216&manufacturer_id=0&tid=f6c1250eitw-rk# I can't see it on the compatability list ... but that doesn't mean that it doesn't work: * it could work, but it isn't on the list * it could be listed under a different (perhaps US) part number Can any one please tell

...sectors), %dx + popw %cx /* write two nibbles */ + call write_hex_value + +partition_table_scan: + movw $partition_table, %si + movw $0x04, %cx /* number of table entries */ + +partition_entry_next: + testb $flag_active, (%si) /* is active (bootable) flag set? */ + jnz msg_partition_active + + addw $16, %si /* next entry */ + loopw partition_entry_next + + jmp print_boot_message /* no active parition, so don't try to read a sector */ + +msg_partition_active: + movb $0x05, %ch /* convert CL countdown to partition number */ + subb %cl, %ch /* CL:partition translations 4:1, 3:2, 2:3, 1...

More specifically there is no instruction that can add/subtract segment registers. They can only be updated my the mov segment register instructions, opcodes 0x8c and 0x8e in x86 assembly. I suggest you write the text version of the assembly you want to generate and assemble it with llvm-mc. This will tell you if its even valid. After that you can use -show-inst to print the names of the

...sectors), %dx + popw %cx /* write two nibbles */ + call write_hex_value + +partition_table_scan: + movw $partition_table, %si + movw $0x04, %cx /* number of table entries */ + +partition_entry_next: + testb $flag_active, (%si) /* is active (bootable) flag set? */ + jnz msg_partition_active + + addw $16, %si /* next entry */ + loopw partition_entry_next + + jmp print_boot_message /* no active parition */ + +msg_partition_active: + movb $0x05, %ch /* convert CL countdown to partition number */ + subb %cl, %ch /* CL:partition translations 4:1, 3:2, 2:3, 1:4 */ + movb %ch, %dl /* value to...

Hi, I have a Liebert GXT2-1000RT230 UPS that is connected to my server using a serial cable. I have no idea to what port exactly it is connected so my first question is: how do I find out what /dev/tty** should I use? Do I need to install a device driver for it? Where do I find it? What should I use and how do I do so the server shuts down if the battery level is low? Yes, I'm a newby,

...sectors), %dx + popw %cx /* write two nibbles */ + call write_hex_value + +partition_table_scan: + movw $partition_table, %si + movw $0x04, %cx /* number of table entries */ + +partition_entry_next: + testb $flag_active, (%si) /* is active (bootable) flag set? */ + jnz msg_partition_active + + addw $16, %si /* next entry */ + loopw partition_entry_next + + jmp print_boot_message /* no active parition, so don't try to read a sector */ + +msg_partition_active: + movb $0x05, %ch /* convert CL countdown to partition number */ + subb %cl, %ch /* CL:partition translations 4:1, 3:2, 2:3, 1...

...call wrstr .ascii " =$PnP\0" scn_pnp: call crlf /* $PnP Scan */ movw $0xf000, %dx pushw %dx popw %es movw $0, %si movw $0x1000, %cx /* 0x506E5024 */ movw $0x5024, %dx movw $0x506E, %bx ch_pnp: es lodsw cmpw %dx, %ax jne ch_pnp_l es lodsw cmpw %bx, %ax je pr_pnp ch_pnp_l: addw $14, %si andw $0xFFF0, %si loopw ch_pnp jmp end pr_pnp: pushw %si call wrstr .ascii "$PnP-\0" movw %es, %dx call wrhexw movb $':, %al call wrchr popw %dx andw $0xFFF0, %dx call wrhexw #endif /* DEBUG_PNP */ call crlf end: jmp bootfail ASCII_MARKER1 "wc" wr...

...for duplication of either patterns or instruction definitions for RV32 and RV64. It's worth noting that RV64I is a different base ISA to RV32I. Rather than adding 64-bit operations, it re-defines the operations as 64-bit and introduces a small number of 'W' suffixed instructions such as ADDW, SLLW etc to operate on 32-bit values. There are some challenges though. Consider the variable-length shifts introduced in RV64I. SLLW, SRLW, and SRAW operate on 32-bit values and produce 32-bit sign-extended results. They read only the lower 5 bits from the shift amount. The following function sh...

Paravirtualized spinlocks produce some overhead even if the kernel is running on bare metal. The main reason are the more complex locking and unlocking functions. Especially unlocking is no longer just one instruction but so complex that it is no longer inlined. This patch series addresses this issue by adding two more pvops functions to reduce the size of the inlined spinlock functions. When

Paravirtualized spinlocks produce some overhead even if the kernel is running on bare metal. The main reason are the more complex locking and unlocking functions. Especially unlocking is no longer just one instruction but so complex that it is no longer inlined. This patch series addresses this issue by adding two more pvops functions to reduce the size of the inlined spinlock functions. When

I have posted a patch that switches the API to one that supports this (yet non-existent functionality) earlier: https://reviews.llvm.org/D24631 The comments from that were incorporated into the following RFC. Motivation: Certain targets feature "variable-sized" registers, i.e. a situation where the register size can be configured by a hardware switch. A common instruction set

I am working on a Linux-based boot disk for my project (http://unattended.sourceforge.net/), and I have hit a snag. Under Linux 2.6, the kernel (via HDIO_GETGEO) always reports the C/H/S geometry of an IDE drive as X/16/63. But most BIOSes want to use the geometry Y/255/63. Most partitioning tools (including Parted) will take clues from an existing partition table and adapt to the BIOS values.

From: Jeremy Fitzhardinge <jeremy.fitzhardinge at citrix.com> Hi all, This is a revised version of the pvticket lock series. The early part of the series is mostly unchanged: it converts the bulk of the ticket lock code into C and makes the "small" and "large" ticket code common. The only changes are the incorporation of various review comments. The latter part of