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...on FPCCtoARMCC, condition ISD::SETO generates ARMCC::VC ( Overflow clear) condition. Thus, if we are able to appropriately generate ISD::SETO inside SDNode for overflow clear and then map it to ARMCC::VC instruction in IntCCtoARMCC, then will that be enough to generate the an instruction like "addvc"? Thanks Regards, Kapil Anand On Mon, Jul 14, 2008 at 6:10 PM, Evan Cheng <evan.cheng at apple.com> wrote: > > On Jul 14, 2008, at 12:59 PM, kapil anand wrote: > > Hi all, > > I am using LLVM compiler and CodeGen for generating ARM binaries. > > I was going t...

...D::SETO generates ARMCC::VC ( Overflow clear) condition. > Thus, if we are able to appropriately generate ISD::SETO inside > SDNode for overflow clear and then map it to ARMCC::VC instruction > in IntCCtoARMCC, then will that be enough to generate the an > instruction like "addvc"? addvc means "executing the add when overflow clear"? Then yes, that will happen as a result of if conversion if the incoming instruction selection input looks like that. Evan > > > Thanks > > Regards, > Kapil Anand > > On Mon, Jul 14, 2008 at 6:10 PM,...

...ition > ISD::SETO generates ARMCC::VC ( Overflow clear) condition. Thus, if we are > able to appropriately generate ISD::SETO inside SDNode for overflow clear > and then map it to ARMCC::VC instruction in IntCCtoARMCC, then will that be > enough to generate the an instruction like "addvc"? > > > addvc means "executing the add when overflow clear"? Then yes, that will > happen as a result of if conversion if the incoming instruction selection > input looks like that. > > Evan > > > > Thanks > > Regards, > Kapil Anand > >...

On Jul 14, 2008, at 12:59 PM, kapil anand wrote: > Hi all, > > I am using LLVM compiler and CodeGen for generating ARM binaries. > > I was going through the code for ARM backend. I noticed that the ARM > Condition field( Bits 31-28) is generated by converting the > conditions used in icmp and branch. For example, if I have following > C Code > > int a,b,c,d;

Hi all, I am using LLVM compiler and CodeGen for generating ARM binaries. I was going through the code for ARM backend. I noticed that the ARM Condition field( Bits 31-28) is generated by converting the conditions used in icmp and branch. For example, if I have following C Code int a,b,c,d; c = a+b; if(c==0) d = a + 10; Then I get ( Assembly Instructions with opcodes only) add *cmp*