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...ebug output: # Before ARMLoadStoreOptimizer: BB#21: derived from LLVM BB %cond.end Live Ins: %LR %R0 %R1 %R7 %R10 %R11 Predecessors according to CFG: BB#14 BB#18 STRi12 %R7<kill>, %R1, 0, pred:14, pred:%noreg; mem:ST4[%first257](tbaa=!"int") %R1<def> = ADDri %R1<kill>, 4, pred:14, pred:%noreg, opt:%CPSR<def> Bcc <BB#23>, pred:0, pred:%CPSR<kill> B <BB#22> Successors according to CFG: BB#23 BB#22 # After ARMLoadStoreOptimizer: BB#21: derived from LLVM BB %cond.end Live Ins: %LR %R0 %R1 %R7 %R10 %R11...

...oreg %2:gprnopc = LDRrs killed %0:gprnopc, %1, 0, 14, %noreg; mem:LD4[JumpTable] BR_JTr killed %2, %jump-table.0 Successors according to CFG: %bb.2(?%) %bb.3(?%) %bb.4(?%) %bb.5(?%) %bb.2: derived from LLVM BB %2 Predecessors according to CFG: %bb.1 %r0 = LDRi12 %stack.2, 14, %noreg %r0 = ADDri %r0, 11, 14, %noreg, %noreg STRi12 %r0, %stack.2, 14, %noreg B %bb.6 Successors according to CFG: %bb.6 %bb.3: derived from LLVM BB %3 Predecessors according to CFG: %bb.1 %r0 = LDRi12 %stack.2, 14, %noreg %r0 = ADDri %r0, 12, 14, %noreg, %noreg STRi12 %r0, %stack.2, 14, %noreg B %bb.6...

...MLoadStoreOptimizer: > BB#21: derived from LLVM BB %cond.end > Live Ins: %LR %R0 %R1 %R7 %R10 %R11 > Predecessors according to CFG: BB#14 BB#18 > STRi12 %R7<kill>, %R1, 0, pred:14, pred:%noreg; mem:ST4[%first257](tbaa=!"int") > %R1<def> = ADDri %R1<kill>, 4, pred:14, pred:%noreg, opt:%CPSR<def> > Bcc <BB#23>, pred:0, pred:%CPSR<kill> > B <BB#22> > Successors according to CFG: BB#23 BB#22 > > # After ARMLoadStoreOptimizer: > BB#21: derived from LLVM BB %cond.end >...

...:gprnopc = LDRrs killed %0:gprnopc, %1, 0, 14, %noreg; mem:LD4[JumpTable] BR_JTr killed %2, %jump-table.0 Successors according to CFG: %bb.2(?%) %bb.3(?%) %bb.4(?%) %bb.5(?%) %bb.2: derived from LLVM BB %2 Predecessors according to CFG: %bb.1 %r0 = LDRi12 %stack.2, 14, %noreg %r0 = ADDri %r0, 11, 14, %noreg, %noreg STRi12 %r0, %stack.2, 14, %noreg B %bb.6 Successors according to CFG: %bb.6 %bb.3: derived from LLVM BB %3 Predecessors according to CFG: %bb.1 %r0 = LDRi12 %stack.2, 14, %noreg %r0 = ADDri %r0, 12, 14, %noreg, %noreg STRi12 %r0, %stack.2, 14, %noreg...

...:gprnopc = LDRrs killed %0:gprnopc, %1, 0, 14, %noreg; mem:LD4[JumpTable] BR_JTr killed %2, %jump-table.0 Successors according to CFG: %bb.2(?%) %bb.3(?%) %bb.4(?%) %bb.5(?%) %bb.2: derived from LLVM BB %2 Predecessors according to CFG: %bb.1 %r0 = LDRi12 %stack.2, 14, %noreg %r0 = ADDri %r0, 11, 14, %noreg, %noreg STRi12 %r0, %stack.2, 14, %noreg B %bb.6 Successors according to CFG: %bb.6 %bb.3: derived from LLVM BB %3 Predecessors according to CFG: %bb.1 %r0 = LDRi12 %stack.2, 14, %noreg %r0 = ADDri %r0, 12, 14, %noreg, %noreg STRi12 %r0, %stack.2, 14, %noreg...

...oreg %2:gprnopc = LDRrs killed %0:gprnopc, %1, 0, 14, %noreg; mem:LD4[JumpTable] BR_JTr killed %2, %jump-table.0 Successors according to CFG: %bb.2(?%) %bb.3(?%) %bb.4(?%) %bb.5(?%) %bb.2: derived from LLVM BB %2 Predecessors according to CFG: %bb.1 %r0 = LDRi12 %stack.2, 14, %noreg %r0 = ADDri %r0, 11, 14, %noreg, %noreg STRi12 %r0, %stack.2, 14, %noreg B %bb.6 Successors according to CFG: %bb.6 %bb.3: derived from LLVM BB %3 Predecessors according to CFG: %bb.1 %r0 = LDRi12 %stack.2, 14, %noreg %r0 = ADDri %r0, 12, 14, %noreg, %noreg STRi12 %r0, %stack.2, 14, %noreg B %bb.6...

...nocapture, %struct.stat.6.13.20.64* nocapture) #1 declare signext i32 @stat(i8* nocapture, %struct.stat.6.13.20.64* nocapture) #1 mi: | BB#0: derived from LLVM BB %entry Live Ins: %I0 %O6<def> = SAVEri %O6, -176 %I1<def> = SETHIi <ga:@Pflag>[TF=3] %I1<def> = ADDri %I1<kill>, <ga:@Pflag>[TF=4] %I1<def> = SLLXri %I1<kill>, 12 %I2<def> = LDUBri %I1<kill>, <ga:@Pflag>[TF=5]; mem:LD1[@Pflag] %I1<def> = SETHIi <ga:@stat>[TF=3] %I1<def> = ADDri %I1<kill>, <ga:@stat>[TF=4] %I1<def> =...

...d4800 JIT: 0x4512e014: %SP<def> = SUBri %SP<kill>, 8, 14, %reg0, %reg0 0xe24dd008 JIT: 0x4512e018: %R0<def> = MOVi 20, 14, %reg0, %reg0 0xe3a00014 JIT: 0x4512e01c: STR %R0<kill>, %SP, %reg0, 4, 14, %reg0, Mem:ST(4,4) [b + 0] 0xe58d0004 JIT: 0x4512e020: %R0<def> = ADDri %SP, 4, 14, %reg0, %reg0 0xe28d0004 JIT: 0x4512e024: BL <ga:add1>, %R0<kill>, %R0<imp-def,dead>, %R1<imp-def,dead>, %R2<imp-def,dead>, %R3<imp-def,dead>, %R12<imp-def,dead>, %LR<imp-def,dead>, %D0<imp-def,dead>, %D1<imp-def,dead>, %D2&lt...

...mp-def,dead>, %d0<imp-def,dead>, %d1<imp-def,dead>, %d2<imp-def,dead>, %d3<imp-def,dead>, %d4<imp-def,dead>, %d5<imp-def,dead>, %d6<imp-def,dead>, %d7<imp-def,dead>, %cpsr<imp-def,dead> %r0 = MOVr %r4<kill>, 14, %NOREG, %NOREG %sp = ADDri %sp<kill>, 12, 14, %NOREG, %NOREG %r4 = LDR <fi#10>, %NOREG, 0, 14, %NOREG %r5 = LDR <fi#9>, %NOREG, 0, 14, %NOREG %r6 = LDR <fi#8>, %NOREG, 0, 14, %NOREG %r7 = LDR <fi#7>, %NOREG, 0, 14, %NOREG %r8 = LDR <fi#6>, %NOREG, 0, 14, %NOREG %r9 = LDR <fi#5>...

...cessor. I get an unusual situation where the code generated for a BB is BB#23: derived from LLVM BB %sw.bb99 Live Ins: %vr2 %vr0 %vr1 %vr9 %vr3 %vr8 %vr4 %vr5 %vr6 Predecessors according to CFG: BB#22 %vr46<def> = LD_Iri %LV, -4; mem:LD4[FixedStack0] %vr7<def> = ADDri %vr9, 1 %vr47<def> = ADDri %vr46, -4 ST_Iri %LV, -4, %vr47<kill>; mem:ST4[%cpArg.addr] >>> %vr48<def> = LD_Iri %vr46<kill>, 0; mem:LD4[<unknown>] ST_Cri %vr9<kill>, 0, %vr48<kill>; mem:ST1[%cpStrBuf.1] %vr8<de...

...BB#21: derived from LLVM BB %cond.end > > Live Ins: %LR %R0 %R1 %R7 %R10 %R11 > > Predecessors according to CFG: BB#14 BB#18 > > STRi12 %R7<kill>, %R1, 0, pred:14, pred:%noreg; > mem:ST4[%first257](tbaa=!"int") > > %R1<def> = ADDri %R1<kill>, 4, pred:14, pred:%noreg, > opt:%CPSR<def> > > Bcc <BB#23>, pred:0, pred:%CPSR<kill> > > B <BB#22> > > Successors according to CFG: BB#23 BB#22 > > > > # After ARMLoadStoreOptimizer: > > BB#21: derive...

...0x8fc2c98, ID#1: Predecessors according to CFG: 0x8fdac90 (#0) %R0<def> = MOVi 0, 14, %reg0, %reg0 *** STR %LR<kill>, %R0<kill>, %reg0, 0, 14, %reg0, Mem:ST(4,4) [0x8fc2d68 + 0] %LR<def> = LDR <fi#0>, %reg0, 0, 14, %reg0 %SP<def> = ADDri %SP<kill>, 4, 14, %reg0, %reg0 BX_RET 14, %reg0 UnifiedReturnBlock: 0x8fdad70, LLVM BB @0x8fc2cc0, ID#2: Predecessors according to CFG: 0x8fdac90 (#0) %LR<def> = LDR <fi#0>, %reg0, 0, 14, %reg0 %SP<def> = ADDri %SP<kill>, 4, 14, %reg0, %reg...

On Aug 16, 2012, at 1:39 PM, Jyotsna Verma <jverma at codeaurora.org> wrote: > Hi Everyone, > > After some more thoughts to the Jacob's suggestion of using multiclasses for > Opcode mapping, this is what I have come up with. Please take a look at the > design below and let me know if you have any suggestions/questions. Hi Jyotsna, You are on to something here, but you

...is not the frame pointer. It's the link register (caller address). It > should be available as a general purpose register. OK. > The bug is elsewhere. It has to do with kill / dead markers. > %LR<def> = LDR <fi#0>, %reg0, 0, 14, %reg0 > %SP<def> = ADDri %SP<kill>, 4, 14, %reg0, %reg0 > BX_RET 14, %reg0 > LR is restored here but it's not killed before the end of the block is > reached. Hmm. I have no idea about what ARM backend does. My register allocator just assigns the registers as I explained in my original mail. Then...

...imp-def,dead>, %D5<imp- def,dead>, %D6<imp-def,dead>, %D7<imp-def,dead>, %CPSR<imp-def,dead> %R0<def> = MOVi 0, 14, %reg0, %reg0 %R7<def> = LDR %SP, %reg0, 0, 14, %reg0 %LR<def> = LDR %SP, %reg0, 4, 14, %reg0 %SP<def> = ADDri %SP<kill>, 8, 14, %reg0, %reg0 BX_RET 14, %reg0, %R0<imp-use,kill>, %LR<imp-use,kill> The LR defined by BL is not killed before the PEI inserted LR restore. The register scavenger doesn't like this. The issue is while BL does modifies LR, it doesn't actually d...

...<imp- > def,dead>, %D6<imp-def,dead>, %D7<imp-def,dead>, %CPSR<imp-def,dead> > %R0<def> = MOVi 0, 14, %reg0, %reg0 > %R7<def> = LDR %SP, %reg0, 0, 14, %reg0 > %LR<def> = LDR %SP, %reg0, 4, 14, %reg0 > %SP<def> = ADDri %SP<kill>, 8, 14, %reg0, %reg0 > BX_RET 14, %reg0, %R0<imp-use,kill>, %LR<imp-use,kill> > > The LR defined by BL is not killed before the PEI inserted LR restore. > The register scavenger doesn't like this. > > The issue is while BL does modifies LR,...

On Wed, Jun 26, 2013 at 3:59 PM, Nadav Rotem <nrotem at apple.com> wrote: > > On Jun 26, 2013, at 3:51 PM, Chandler Carruth <chandlerc at google.com> wrote: > > Can you suggest an alternative solution? Can you describe why you don't > think metadata is the right container? This alone isn't really helpful at > moving us toward something that there has been

...ding to CFG: 0x8fdac90 (#0) >> %R0<def> = MOVi 0, 14, %reg0, %reg0 >> *** STR %LR<kill>, %R0<kill>, %reg0, 0, 14, %reg0, Mem:ST(4,4) >> [0x8fc2d68 + 0] >> %LR<def> = LDR <fi#0>, %reg0, 0, 14, %reg0 >> %SP<def> = ADDri %SP<kill>, 4, 14, %reg0, %reg0 >> BX_RET 14, %reg0 > > Ok, ignore my earlier email about BX_RET. The issue is LR should be added to > livein of BB #1. Who should do it? Do you mean that ARM backend/LiveIntervalsAnalysis/LiveVariables should do it or do you mean that my r...

...to have a new virtual register as part of the stack store process since we don't have indirect adressing. Should we be creating a physical register directly somehow, or can we perhaps signal to the allocator that the basic block's contents are updated? Below is our storeRegToStackSlot, the ADDri instruction is transformed into a copy-add pair in eliminateFrameIndex. void OurTargetInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int Fra...

...redecessors according to CFG: 0x8fdac90 (#0) > %R0<def> = MOVi 0, 14, %reg0, %reg0 > *** STR %LR<kill>, %R0<kill>, %reg0, 0, 14, %reg0, Mem:ST(4,4) > [0x8fc2d68 + 0] > %LR<def> = LDR <fi#0>, %reg0, 0, 14, %reg0 > %SP<def> = ADDri %SP<kill>, 4, 14, %reg0, %reg0 > BX_RET 14, %reg0 Ok, ignore my earlier email about BX_RET. The issue is LR should be added to livein of BB #1. **** Post Machine Instrs **** # Machine code for Insert(): Live Ins: R0 in VR#1025 R1 in VR#1026 entry: 0x8fdac90, LLVM BB @0x8fc2c48...