Displaying 4 results from an estimated 4 matches for "addr_sh".
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addr_sz
2016 Sep 26
2
Incompatible type assertion from llvm-tblgen
...LoadOpIdx< bits<7> op,
string instr_asm,
OperandInfo info,
InstrItinClass itin=II_LOAD1_RR >
//
// load: r1 = mem[r2 + (r3 << sizeof(operand) ]
//
: FR3< op,
(outs info.regClass:$r1),
(ins ADDR_SHLI:$addr), //<<-this line causes assert
instr_asm # "\t\t$r1, $addr, " # info.sizeStr,
[(set info.regClass:$r1, (load ADDR_SHLI:$addr))],
itin > {
}
The other related definitions are:
// This class provides load/store address format selection supp...
2016 Sep 28
2
Incompatible type assertion from llvm-tblgen
...x16(addrspace=4)](align=8)(tbaa=<0x3082188>)> [ORD=4]
And map it to a load.idx instruction with the following semantics:
load.idx r1,r2,r3,SIZE r1 <- mem[r2 + (r3 << sizeof(operand))]
That somehow the pattern matching dag fragment would need to be something
like I had in ADDR_SHLI definition:
def ADDR_SHLI : Addr< 2, "SelectAddrShlImm",
(ops GPRC:$base, ( shl GPRC:$offsetreg, (i64 3))) >;
Now If I have to create a subclass of Operand and define it's EncoderMethod
in C++, does that mean the pattern matching (matching the shift l...
2016 Sep 26
2
Incompatible type assertion from llvm-tblgen
...i64imm:$offsetimm) >;
Do I need to create some other intermediate node type for a shifted address?
Phil
On Mon, Sep 26, 2016 at 1:42 PM, Krzysztof Parzyszek via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> On 9/26/2016 3:36 PM, Phil Tomson via llvm-dev wrote:
>
>> def ADDR_SHLI : Addr< 2, "SelectAddrShlImm",
>> (ops GPRC:$base, ( shl GPRC:$offsetreg, (i64 3))) >;
>>
>
> You have a dag in the list of operands. That won't work.
>
> -Krzysztof
>
> --
> Qualcomm Innovation Center, Inc. is a member of...
2016 Oct 04
2
Incompatible type assertion from llvm-tblgen
...l Tomson wrote:
>
>> And map it to a load.idx instruction with the following semantics:
>> load.idx r1,r2,r3,SIZE r1 <- mem[r2 + (r3 << sizeof(operand))]
>>
>> That somehow the pattern matching dag fragment would need to be
>> something like I had in ADDR_SHLI definition:
>> def ADDR_SHLI : Addr< 2, "SelectAddrShlImm",
>> (ops GPRC:$base, ( shl GPRC:$offsetreg, (i64 3))) >;
>>
>>
>> Now If I have to create a subclass of Operand and define it's
>> EncoderMethod in C++, does...