search for: addr_args

...s_ucode_msgqueue.c index 6f10b09..2da147b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c @@ -80,12 +80,12 @@ acr_ls_msgqueue_post_run(struct nvkm_msgqueue *queue, struct nvkm_falcon *falcon, u32 addr_args) { struct nvkm_device *device = falcon->owner->device; - u32 cmdline_size = NVKM_MSGQUEUE_CMDLINE_SIZE; - u8 buf[cmdline_size]; + u8 buf[NVKM_MSGQUEUE_CMDLINE_SIZE]; - memset(buf, 0, cmdline_size); + memset(buf, 0, NVKM_MSGQUEUE_CMDLINE_SIZE); nvkm_msgqueue_write_cmdline(queue, buf); -...

...gt;trace_buf.obj), pmuvm->vm, + NV_MEM_ACCESS_RW, &priv->trace_buf.vma); + if (ret) + return ret; + + return 0; +} + +static int +gk20a_pmu_bootstrap(struct gk20a_pmu_priv *priv) +{ + struct pmu_ucode_desc *desc = priv->desc; + u32 addr_code, addr_data, addr_load; + u32 i, blocks, addr_args; + struct pmu_cmdline_args_gk20a cmdline_args; + struct nvkm_pmu_priv_vm *pmuvm = &priv->pmuvm; + + nv_mask(priv, 0x0010a048, 0x01, 0x01); + /*bind the address*/ + nv_wr32(priv, 0x0010a480, + pmuvm->mem->addr >> 12 | + 0x1 << 30 | + 0x20000000); + + /* TBD: load all othe...

...147b 100644 >> --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c >> +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c >> @@ -80,12 +80,12 @@ acr_ls_msgqueue_post_run(struct nvkm_msgqueue *queue, >> struct nvkm_falcon *falcon, u32 addr_args) >> { >> struct nvkm_device *device = falcon->owner->device; >> - u32 cmdline_size = NVKM_MSGQUEUE_CMDLINE_SIZE; >> - u8 buf[cmdline_size]; >> + u8 buf[NVKM_MSGQUEUE_CMDLINE_SIZE]; >> >> - memset(buf, 0, cmdline_size); >> + memset(buf, 0, N...

...ndex 6f10b09..2da147b 100644 > --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c > +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c > @@ -80,12 +80,12 @@ acr_ls_msgqueue_post_run(struct nvkm_msgqueue *queue, > struct nvkm_falcon *falcon, u32 addr_args) > { > struct nvkm_device *device = falcon->owner->device; > - u32 cmdline_size = NVKM_MSGQUEUE_CMDLINE_SIZE; > - u8 buf[cmdline_size]; > + u8 buf[NVKM_MSGQUEUE_CMDLINE_SIZE]; > > - memset(buf, 0, cmdline_size); > + memset(buf, 0, NVKM_MSGQUEUE_CMDLINE_SIZE); >...

...: + return 0; +map_err: + nvkm_gpuobj_destroy(pmu->trace_buf.obj); +err: + return err; +} + +static int +pmu_bootstrap(struct gk20a_pmu_priv *pmu) +{ + struct nvkm_pmu *ppmu = &pmu->base; + struct pmu_ucode_desc *desc = pmu->desc; + u32 addr_code, addr_data, addr_load; + u32 i, blocks, addr_args; + struct pmu_cmdline_args_gk20a cmdline_args; + struct nvkm_pmu_priv_vm *ppmuvm = &pmu->pmuvm; + nv_mask(ppmu, 0x0010a048, 0x01, 0x01); + /*bind the address*/ + nv_wr32(ppmu, 0x0010a480, + ppmuvm->mem->addr >> 12 | + 0x1 << 30 | + 0x20000000); + + /* TBD: load all other...

...s_ucode_msgqueue.c index 6f10b09..1e1f1c6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c @@ -80,12 +80,11 @@ acr_ls_msgqueue_post_run(struct nvkm_msgqueue *queue, struct nvkm_falcon *falcon, u32 addr_args) { struct nvkm_device *device = falcon->owner->device; - u32 cmdline_size = NVKM_MSGQUEUE_CMDLINE_SIZE; - u8 buf[cmdline_size]; + u8 buf[NVKM_MSGQUEUE_CMDLINE_SIZE]; - memset(buf, 0, cmdline_size); + memset(buf, 0, sizeof(buf)); nvkm_msgqueue_write_cmdline(queue, buf); - nvkm_falcon_lo...

...gt;> + >> + return 0; >> +} >> + >> +static int >> +gk20a_pmu_bootstrap(struct gk20a_pmu_priv *priv) >> +{ >> + struct pmu_ucode_desc *desc = priv->desc; >> + u32 addr_code, addr_data, addr_load; >> + u32 i, blocks, addr_args; >> + struct pmu_cmdline_args_gk20a cmdline_args; >> + struct nvkm_pmu_priv_vm *pmuvm = &priv->pmuvm; >> + >> + nv_mask(priv, 0x0010a048, 0x01, 0x01); >> + /*bind the address*/ >> + nv_wr32(priv, 0x0010a480, >> +...

...are_mem_target > > > > from NVKM_MEM_TARGET_HOST to NVKM_MEM_TARGET_NCOH ? > > > In addition to Dave's change, can you try changing the > > nvkm_falcon_load_dmem() call in gm20b_pmu_init() to: > > > > nvkm_falcon_pio_wr(falcon, (u8 *)&args, 0, 0, DMEM, addr_args, > > sizeof(args), 0, false); > > Hello! > > Chiming in just to say that with this change I see the same as Nicolas > except that the init message size is 255 instead of 0: > > [ 2.196934] nouveau 57000000.gpu: pmu: unexpected init message size 255 vs 42 I've attac...

...ARGET_HOST to NVKM_MEM_TARGET_NCOH ? > > > > > > > In addition to Dave's change, can you try changing the > > > > nvkm_falcon_load_dmem() call in gm20b_pmu_init() to: > > > > > > > > nvkm_falcon_pio_wr(falcon, (u8 *)&args, 0, 0, DMEM, addr_args, > > > > sizeof(args), 0, false); > > > > > > Chiming in just to say that with this change I see the same as Nicolas > > > except that the init message size is 255 instead of 0: > > > > > > [ 2.196934] nouveau 57000000.gpu: pmu: unexpected...

GP10B is the chip used in Tegra X2 SoCs. This patchset adds support for its base engines after reworking secboot a bit to accomodate its calling convention better. This patchset has been tested rendering simple off-screen buffers using Mesa and yielded the expected result. Alexandre Courbot (15): secboot: allow to boot multiple falcons secboot: pass instance to LS firmware loaders secboot:

...gt; +static int pmu_bootstrap(struct pmu_desc *pmu) > +{ > + struct nvkm_pmu *ppmu = (void *)nvkm_pmu((void *) > + impl_from_pmu(pmu)); > + struct pmu_ucode_desc *desc = pmu->desc; > + u64 addr_code, addr_data, addr_load; > + u32 i, blocks, addr_args; > + u32 *adr_data, *adr_load, *adr_code; > + struct pmu_cmdline_args_gk20a cmdline_args; > + struct pmu_priv_vm *ppmuvm = &pmuvm; > + > + nv_wr32(ppmu, 0x0010a048, > + nv_rd32(ppmu, 0x0010a048) | 0x01); > + /*bind the address*/ &...

..._enable(ppmu, pmc, true); + if (err) + return err; + + return 0; +} + +static int pmu_bootstrap(struct pmu_desc *pmu) +{ + struct nvkm_pmu *ppmu = (void *)nvkm_pmu((void *) + impl_from_pmu(pmu)); + struct pmu_ucode_desc *desc = pmu->desc; + u64 addr_code, addr_data, addr_load; + u32 i, blocks, addr_args; + u32 *adr_data, *adr_load, *adr_code; + struct pmu_cmdline_args_gk20a cmdline_args; + struct pmu_priv_vm *ppmuvm = &pmuvm; + + nv_wr32(ppmu, 0x0010a048, + nv_rd32(ppmu, 0x0010a048) | 0x01); + /*bind the address*/ + nv_wr32(ppmu, 0x0010a480, + ppmuvm->mem->addr >> 12 | + 0x1 &lt...

...gt; +static int pmu_bootstrap(struct pmu_desc *pmu) > +{ > + struct nvkm_pmu *ppmu = (void *)nvkm_pmu((void *) > + impl_from_pmu(pmu)); > + struct pmu_ucode_desc *desc = pmu->desc; > + u64 addr_code, addr_data, addr_load; > + u32 i, blocks, addr_args; > + u32 *adr_data, *adr_load, *adr_code; > + struct pmu_cmdline_args_gk20a cmdline_args; > + struct pmu_priv_vm *ppmuvm = &pmuvm; > + > + nv_wr32(ppmu, 0x0010a048, > + nv_rd32(ppmu, 0x0010a048) | 0x01); > + /*bind the address*/ &...

This revision includes initial signed PMU firmware support for GM20B (Tegra X1). This PMU code will also be used as a basis for dGPU signed PMU firmware support. With the PMU code, the refactoring of secure boot should also make more sense. ACR (secure boot) support is now separated by the driver version it originates from. This separation allows to run any version of the ACR on any chip,