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...its on the stack and the default logic provided in LegalizeDAG does not use that convention. Specifically, for these targets we have: setOperationAction(ISD::VAARG, MVT::Other, Expand); I thought that I could solve this problem by: setOperationAction(ISD::VAARG, MVT::i1, Promote); AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64); setOperationAction(ISD::VAARG, MVT::i8, Promote); AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64); setOperationAction(ISD::VAARG, MVT::i16, Promote); AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64); setOperationAction(ISD::VAARG,...

...t; provided in LegalizeDAG does not use that convention. Specifically, > > for these targets we have: setOperationAction(ISD::VAARG, > > MVT::Other, Expand); I thought that I could solve this problem by: > > setOperationAction(ISD::VAARG, MVT::i1, Promote); > > AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64); > > setOperationAction(ISD::VAARG, MVT::i8, Promote); > > AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64); > > setOperationAction(ISD::VAARG, MVT::i16, Promote); > > AddPromotedToType (ISD::VAARG, MVT::i16, MVT:...

...ault logic provided in LegalizeDAG does > not use that convention. Specifically, for these targets we have: > setOperationAction(ISD::VAARG, MVT::Other, Expand); > I thought that I could solve this problem by: > setOperationAction(ISD::VAARG, MVT::i1, Promote); > AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64); > setOperationAction(ISD::VAARG, MVT::i8, Promote); > AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64); > setOperationAction(ISD::VAARG, MVT::i16, Promote); > AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64); > s...

...LegalizeDAG does not use that convention. Specifically, >>> for these targets we have: setOperationAction(ISD::VAARG, >>> MVT::Other, Expand); I thought that I could solve this problem by: >>> setOperationAction(ISD::VAARG, MVT::i1, Promote); >>> AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64); >>> setOperationAction(ISD::VAARG, MVT::i8, Promote); >>> AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64); >>> setOperationAction(ISD::VAARG, MVT::i16, Promote); >>> AddPromotedToType (ISD::VAARG...

On my target store/load of f32 or i32 are equivalents. Previously I had duplicate instructions def in .td to map f32 and i32 to the same opcode. I deleted all that and I instead tried a new approach (to simplify things) : setOperationAction(ISD::STORE, MVT::f32, Promote); AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32); setOperationAction(ISD::LOAD, MVT::f32, Promote); AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32); Now SelectionDAGLegalize::LegalizeDAG() get stuck into an infinite loop. What is going on? I still have the following:(but I think that's fine) addRegist...

...tore/load of f32 or i32 are equivalents. > Previously I had duplicate instructions def in .td to map f32 and i32 to > the same opcode. > > I deleted all that and I instead tried a new approach (to simplify things) : > > setOperationAction(ISD::STORE, MVT::f32, Promote); > AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32); > setOperationAction(ISD::LOAD, MVT::f32, Promote); > AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32); > > Now SelectionDAGLegalize::LegalizeDAG() get stuck into an infinite loop. > What is going on? > > I still have the following:(but I...

...s. > > Previously I had duplicate instructions def in .td to map f32 and i32 to > > the same opcode. > > > > I deleted all that and I instead tried a new approach (to simplify > things) : > > > > setOperationAction(ISD::STORE, MVT::f32, Promote); > > AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32); > > setOperationAction(ISD::LOAD, MVT::f32, Promote); > > AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32); > > > > Now SelectionDAGLegalize::LegalizeDAG() get stuck into an infinite loop. > > What is going on? > > > >...

Is there a way to force llvm to promote all smaller types to i32 instead of i16? Thanks, Micah Villmow Systems Engineer Advanced Technology & Performance Advanced Micro Devices Inc. S1-609 One AMD Place Sunnyvale, CA. 94085 P: 408-749-3966 -------------- next part -------------- An HTML attachment was scrubbed... URL:

...ependent nodes to one particular type. See X86ISelLowering.cpp: // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned) MVT::v2i64; VT++) { setOperationAction(ISD::AND, (MVT::ValueType)VT, Promote); AddPromotedToType (ISD::AND, (MVT::ValueType)VT, MVT::v2i64); ... Evan > > Thanks > -- > Christopher Lamb > > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/...

Hi All, I'm working on a back end for an architecture that makes use of multi- typed register classes. def MR: RegisterClass<"namespace", [type1, type2, ... ], ... > When running some preliminary tests I found that the instruction selector refused to select certain ops (specifically stores) for some instructions when the operand type wasn't the first type for the

...er. Does the "set" (keyword?) translates to an output of the add node, or just another node? Thanks, Patosga 2016-06-06 6:22 GMT+01:00 Nemanja Ivanovic <nemanja.i.ibm at gmail.com>: > > Hi Patosga, > you can control what type the operands are promoted to as follows: > AddPromotedToType (ISD::ADD, MVT::i1, MVT::i64); > > For the "Expand" case, I believe you'll find what you're looking for in > the file: > lib/CodeGen/SelectionDAG/LegalizeDAG.cpp > and function SelectionDAGLegalize::ExpandNode(), but if I'm wrong here > perhaps others can co...

Sorry, glad I'm in the right place. Before I start, I want to state that I'm a beginer and I'm trying to develop a backend by adapting an existent target to my platform. My first doubt is about the SelectionDAG and the TargetLowering class. When I use, for example: setOperationAction(ISD::ADD, MVT::i1, Promote); Is it correct to say that I'm promoting any operand used by the

...SimpleValueType>::const_iterator PTTI = PromoteToType.find(std::make_pair(Op, VT.getSimpleVT().SimpleTy)); if (PTTI != PromoteToType.end()) return PTTI->second; assert((VT.isInteger() || VT.isFloatingPoint()) && "Cannot autopromote this type, add it with AddPromotedToType."); EVT NVT = VT; do { NVT = (MVT::SimpleValueType)(NVT.getSimpleVT().SimpleTy+1); assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid && "Didn't find type to promote to!"); } while (!isTypeLegal(NVT) ||...

...SimpleValueType>::const_iterator PTTI = PromoteToType.find(std::make_pair(Op, VT.getSimpleVT().SimpleTy)); if (PTTI != PromoteToType.end()) return PTTI->second; assert((VT.isInteger() || VT.isFloatingPoint()) && "Cannot autopromote this type, add it with AddPromotedToType."); EVT NVT = VT; do { NVT = (MVT::SimpleValueType)(NVT.getSimpleVT().SimpleTy+1); assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid && "Didn't find type to promote to!"); } while (!isTypeLegal(NVT) ||...

...PTTI = > PromoteToType.find(std::make_pair(Op, > VT.getSimpleVT().SimpleTy)); > if (PTTI != PromoteToType.end()) return PTTI->second; > > assert((VT.isInteger() || VT.isFloatingPoint()) && > "Cannot autopromote this type, add it with > AddPromotedToType."); > > EVT NVT = VT; > do { > NVT = (MVT::SimpleValueType)(NVT.getSimpleVT().SimpleTy+1); > assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid && > "Didn't find type to promote to!"); > } whi...

...; another node? >> >> Thanks, >> Patosga >> >> 2016-06-06 6:22 GMT+01:00 Nemanja Ivanovic <nemanja.i.ibm at gmail.com>: >>> >>> >>> Hi Patosga, >>> you can control what type the operands are promoted to as follows: >>> AddPromotedToType (ISD::ADD, MVT::i1, MVT::i64); >>> >>> For the "Expand" case, I believe you'll find what you're looking for in >>> the file: >>> lib/CodeGen/SelectionDAG/LegalizeDAG.cpp >>> and function SelectionDAGLegalize::ExpandNode(), but if I'...

...PTTI = > PromoteToType.find(std::make_pair(Op, > VT.getSimpleVT().SimpleTy)); > if (PTTI != PromoteToType.end()) return PTTI->second; > > assert((VT.isInteger() || VT.isFloatingPoint()) && > "Cannot autopromote this type, add it with > AddPromotedToType."); > > EVT NVT = VT; > do { > NVT = (MVT::SimpleValueType)(NVT.getSimpleVT().SimpleTy+1); > assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid && > "Didn't find type to promote to!"); > } whi...

...type. See X86ISelLowering.cpp: > > // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to > v2i64. > for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned) > MVT::v2i64; VT++) { > setOperationAction(ISD::AND, (MVT::ValueType)VT, Promote); > AddPromotedToType (ISD::AND, (MVT::ValueType)VT, > MVT::v2i64); > ... > > Evan Thanks Evan, I had tried something like this, but ran into some problems. llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1478: failed assertion `MVT::isVector(VT) && "Cannot promote this load!&quot...

I don't know how your target architecture looks like, but I suspect that <4 x i8> should not be legalized to <1 x i32>. I think that what you are seeing is that <4 x i8> is first split into <2 x i8>, and later promoted to <2 x i32>. At the moment different targets can only affect type-legalization by declaring different legal types. A number of us discussed the

Sorry, <4 x i8> should convert to a <1 x i32>. What currently is happening is that it is returning a <2 x i32> because <1 x i32> does not exist. Micah > -----Original Message----- > From: Rotem, Nadav [mailto:nadav.rotem at intel.com] > Sent: Monday, July 30, 2012 10:51 AM > To: Villmow, Micah; Developers Mailing List > Subject: RE: Vector promotion broken