search for: addpreemitpasses

Oops! No need of Call Graph! In fact, what I want to do is to find which function is the kernel function and which function is called by that kernel. Since OpenCL will make all functions called by kernels inline, I can use function attribute: Noinline to distinguish them. Sorry for bothering you. Antony Yu -- View this message in context:

Are you sure you are initializing your pass properly? Can you show a stripped down version of your pass? On Fri, Jun 21, 2013 at 7:27 AM, Anthony Yu <swpenim at gmail.com> wrote: > Hello, > > I want to write a modulePass in addPreEmitPass() for NVPTX, but I > encounter an assertion failed when executing clang. > > Here is my error message. > ==== > Pass 'NVPTX

I write my pass in a mix way of NVPTXAllocaHoisting, NVPTXSplitBBatBar and transforms/Hello. The following is part of the codes: in NVPTXTargetMachine.cpp bool NVPTXPassConfig::addPreEmitPass() { addPass(createTest()); return false; } in NVPTXTest.h namespace llvm{

Hello, I want to write a modulePass in addPreEmitPass() for NVPTX, but I encounter an assertion failed when executing clang. Here is my error message. ==== Pass 'NVPTX Assembly Printer' is not initialized. Verify if there is a pass dependency cycle. Required Passes: llc: /home/pyyu/local/llvm/lib/IR/PassManager.cpp:637: void llvm::PMTopLevelManager::schedulePass(llvm::Pass*): Assertion

Sorry for the delay. Yeah, that error message is a bit confusing. What's happening is that your pass sequence is invalid. Once the IR has been lowered to machine code, its too late to run LLVM IR passes (ModulePass, FunctionPass, CallGraphSCCPass, etc.). At that point, you need to run a Machine*Pass, e.g. MachineFunctionPass. If you need to run an IR level pass, you need to use

So that's how it is !! Thanks! Hmm, in fact, I want to get Call Graph information in machine code stage, is there any way to get this? I try CallGraph &g= getAnalysis<CallGraph>, but it prints the same error and doesn't work as expected. Antony Yu Justin Holewinski-2 wrote > Sorry for the delay. Yeah, that error message is a bit confusing. What's > happening is

You shouldn't rely on that, its an implementation detail. Instead, you can trace back to the original Function object and check for kernel metadata. See http://llvm.org/docs/NVPTXUsage.html#marking-functions-as-kernels On Tue, Jun 25, 2013 at 11:09 AM, Antony Yu <swpenim at gmail.com> wrote: > Oops! No need of Call Graph! > In fact, what I want to do is to find which function

I try to use INITIALIZE_PASS instead of RegisterPass<> to register my pass, though I don't understand what's their difference and how it works because its documents doesn't exist. But it still doesn't work. Parts of my codes is as follows: in NVPTXTest.h namespace llvm { void initializeNVPTXTestPass(PassRegistry &r); class NVPTXTest : public ModulePass { public:

Hi, We are getting ready to implement several heuristics for correctly using LEAs to avoid stalls in the address generator on Atom. Our plan is to: 1. Disabling LEA generation on Atom in X86ISelDAGToDAG:: SelectLEAAddr() for all but a few pseudo-instructions 2. Identify loads and stores in a X86PassConfig::addPreEmitPass() pass and examine several preceding instructions to

for ARM constant islands and Mips constant islands, the constant islands pass is registered as an addPreEmitPass. for mips at least, it ends of up getting called twice by the pass manager. why is that?

On 1/7/2013 2:15 PM, Xu Liu wrote: > > This would be ideal. How can I do the instrumentation pass after the > instruction scheduling? You could derive your own class from TargetPassConfig, and add the annotation pass in YourDerivedTargetPassConfig::addPreEmitPass. This will add your annotation pass very late, just before the final code is emitted. If you're using the X86 target,

Hi, I want to add Target Specific MachineFunctionPass so that it will run during Link Time Optimization. The pass is currently running in non-LTO compilation (added in addPreEmitPass). What do I need to do in order to run my pass also during LTO? Thanks, Oren --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may

Hi, Here is an update on our proposal to improve the uses of LEA on Atom processors. 1. Disable current generation of LEAs Due to a 3 cycle stall between the ALU and the AGU any address generation done using math instruction will cause a stall on loads and stores which are within 3 cycles of the address generation. Consequently, the heuristics for using LEAs efficiently must know how many

...This makes sense and has come up before in discussions. I can envision a set of analyses that need to run after all MI modification but before asm printing. The StackMapLiveness pass is one such example. No enforcement mechanism exists yet, but it’s safe to say that nothing with modify MI after the addPreEmitPasses hook. For now you can just schedule your pass at the end with comments. > > We could introduce a fake MI analysis that should be invalidated by any pass that mutates the MI. Then check that it’s valid during code emission. That part is trivial. > > I think the real issue is that MC lo...

Was there any development on this? I noticed that clang still produces a lea for the testcase in llvm.org/pr13320. On 28 September 2012 11:36, Nowicki, Tyler <tyler.nowicki at intel.com> wrote: > Hi, > > > > Here is an update on our proposal to improve the uses of LEA on Atom > processors. > > > > 1. Disable current generation of LEAs > > > > Due to

Hi, I would like to execute a MachineFunctionPass after all other passes which modify the machine code. In other words, if we call llc to generate assembly file, that pass should run right before the "Assembly Printer" pass. Is there any official way to enforce this ? Best regards, Sebastien

I'm using a Hexagon's packetizer as an example to packetize instructions for my custom VLIW. The problem that I'm facing is that my target as it turns out doesn't have all the instructions expanded by the time packetization happens (for example I have a RET instruction which gets expanded into a write to a register and a jump/branch). I'm wondering if Hexagon is experiencing

Hello, I want to add assembly instructions at certain points in a function. This is X86 specific. So I am working in the lib/Target/X86 folder. I create a `MachineFunctionPass` in that folder. I register it in the X86TargetMachine.cpp in addPreEmitPass(). I use BuildMI to insert my own assembly instructions in the MachineFunctionPass. This works and my assembly instructions are inserted at

Hi Anton, I ran llc with -verify-coalescing. There were no error messages. Then I added code in MipsPassConfig::addPreEmitPass() to prevent machine verifier from running post delay -slot-filler, and ran llc again. Again, there were no error messages. This is the list of passes run after post-RA scheduling. machine verifier is run twice after post RA scheduler (and CriticalAntiDepBreaker) is run.

Dear developers. My question is the same as the title. Is there any way to implement target specific optimizations after instruction selection or later? I cannot find any related document. Please let me know. Thanks in advance. Minwook Ahn -------------- next part -------------- An HTML attachment was scrubbed... URL: