search for: addpreemitpass

...hich function is called by that kernel. Since OpenCL will make all functions called by kernels inline, I can use function attribute: Noinline to distinguish them. Sorry for bothering you. Antony Yu -- View this message in context: http://llvm.1065342.n5.nabble.com/About-writing-a-modulePass-in-addPreEmitPass-for-NVPTX-tp58701p58839.html Sent from the LLVM - Dev mailing list archive at Nabble.com.

Are you sure you are initializing your pass properly? Can you show a stripped down version of your pass? On Fri, Jun 21, 2013 at 7:27 AM, Anthony Yu <swpenim at gmail.com> wrote: > Hello, > > I want to write a modulePass in addPreEmitPass() for NVPTX, but I > encounter an assertion failed when executing clang. > > Here is my error message. > ==== > Pass 'NVPTX Assembly Printer' is not initialized. > Verify if there is a pass dependency cycle. > Required Passes: > llc: /home/pyyu/local/llvm/lib/IR/Pass...

I write my pass in a mix way of NVPTXAllocaHoisting, NVPTXSplitBBatBar and transforms/Hello. The following is part of the codes: in NVPTXTargetMachine.cpp bool NVPTXPassConfig::addPreEmitPass() { addPass(createTest()); return false; } in NVPTXTest.h namespace llvm{ class NVPTXTest : public ModulePass { void getAnalysisUsage(AnalysisUsage &AU) const {...

Hello, I want to write a modulePass in addPreEmitPass() for NVPTX, but I encounter an assertion failed when executing clang. Here is my error message. ==== Pass 'NVPTX Assembly Printer' is not initialized. Verify if there is a pass dependency cycle. Required Passes: llc: /home/pyyu/local/llvm/lib/IR/PassManager.cpp:637: void llvm::PMTopLevelM...

...'t work, > but this time it tells me that my CallGraphSCCPass is not initialized > instead of 'NVPTX Assembly Printer'. > It's really weird... > > > > > -- > View this message in context: > http://llvm.1065342.n5.nabble.com/About-writing-a-modulePass-in-addPreEmitPass-for-NVPTX-tp58701p58770.html > Sent from the LLVM - Dev mailing list archive at Nabble.com. > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev &g...

...______________________________________________ > LLVM Developers mailing list > LLVMdev at .uiuc > http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev -- View this message in context: http://llvm.1065342.n5.nabble.com/About-writing-a-modulePass-in-addPreEmitPass-for-NVPTX-tp58701p58813.html Sent from the LLVM - Dev mailing list archive at Nabble.com.

...ll make all > functions called by kernels inline, I can use function attribute: Noinline > to distinguish them. > > Sorry for bothering you. > > Antony Yu > > > > -- > View this message in context: > http://llvm.1065342.n5.nabble.com/About-writing-a-modulePass-in-addPreEmitPass-for-NVPTX-tp58701p58839.html > Sent from the LLVM - Dev mailing list archive at Nabble.com. > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev &g...

...ay to write a CallGraphSCCPass, it still doesn't work, but this time it tells me that my CallGraphSCCPass is not initialized instead of 'NVPTX Assembly Printer'. It's really weird... -- View this message in context: http://llvm.1065342.n5.nabble.com/About-writing-a-modulePass-in-addPreEmitPass-for-NVPTX-tp58701p58770.html Sent from the LLVM - Dev mailing list archive at Nabble.com.

...y to implement several heuristics for correctly using LEAs to avoid stalls in the address generator on Atom. Our plan is to: 1. Disabling LEA generation on Atom in X86ISelDAGToDAG:: SelectLEAAddr() for all but a few pseudo-instructions 2. Identify loads and stores in a X86PassConfig::addPreEmitPass() pass and examine several preceding instructions to determine if an add, subtract, or mov can profitably be turned into an LEA. The heuristics for using LEAs efficiently must know how many cycles pass between the generation of an address and its use. This requires LEAs to be added after schedulin...

for ARM constant islands and Mips constant islands, the constant islands pass is registered as an addPreEmitPass. for mips at least, it ends of up getting called twice by the pass manager. why is that?

On 1/7/2013 2:15 PM, Xu Liu wrote: > > This would be ideal. How can I do the instrumentation pass after the > instruction scheduling? You could derive your own class from TargetPassConfig, and add the annotation pass in YourDerivedTargetPassConfig::addPreEmitPass. This will add your annotation pass very late, just before the final code is emitted. If you're using the X86 target, then the class and the function is already there: lib/Target/X86/X86TargetMachine.cpp: bool X86PassConfig::addPreEmitPass() { bool ShouldPrint = false; if (getOptLe...

Hi, I want to add Target Specific MachineFunctionPass so that it will run during Link Time Optimization. The pass is currently running in non-LTO compilation (added in addPreEmitPass). What do I need to do in order to run my pass also during LTO? Thanks, Oren --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review...

...tly must know how many cycles pass between the address generation and its use. However, currently LEAs are inserted before this information is known (ie before register allocation). Part of the attached patch disables the current generation of LEAs. 2. Identify loads and stores in a X86PassConfig::addPreEmitPass() pass We will use an addPreEmitPass pass, similar to the VZeroUpper pass. For each load/store found we will identify its address and index, and examine previous instructions to identify where they are being generated to identify opportunities for LEAs. 3. Replacing instructions with LEAs Instru...

...This makes sense and has come up before in discussions. I can envision a set of analyses that need to run after all MI modification but before asm printing. The StackMapLiveness pass is one such example. No enforcement mechanism exists yet, but it’s safe to say that nothing with modify MI after the addPreEmitPasses hook. For now you can just schedule your pass at the end with comments. > > We could introduce a fake MI analysis that should be invalidated by any pass that mutates the MI. Then check that it’s valid during code emission. That part is trivial. > > I think the real issue is that MC...

...between the address > generation and its use. However, currently LEAs are inserted before this > information is known (ie before register allocation). Part of the attached > patch disables the current generation of LEAs. > > > > 2. Identify loads and stores in a X86PassConfig::addPreEmitPass() pass > > > > We will use an addPreEmitPass pass, similar to the VZeroUpper pass. For each > load/store found we will identify its address and index, and examine > previous instructions to identify where they are being generated to identify > opportunities for LEAs. > >...

Hi, I would like to execute a MachineFunctionPass after all other passes which modify the machine code. In other words, if we call llc to generate assembly file, that pass should run right before the "Assembly Printer" pass. Is there any official way to enforce this ? Best regards, Sebastien

...a write to a register and a jump/branch). I'm wondering if Hexagon is experiencing the same issue and how it is solved? And if it doesn't experience the same what would be the recommendation on solving this problem? At the moment, my packetization pass is the last one in MyTargetPassConfig::addPreEmitPass() Any help is appreciated. -- R -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20151117/47d2419c/attachment.html>

Hello, I want to add assembly instructions at certain points in a function. This is X86 specific. So I am working in the lib/Target/X86 folder. I create a `MachineFunctionPass` in that folder. I register it in the X86TargetMachine.cpp in addPreEmitPass(). I use BuildMI to insert my own assembly instructions in the MachineFunctionPass. This works and my assembly instructions are inserted at desired places. However, this breaks the alignment. So when I run the generated code, I get segmentation fault (precisely in printf with XMM registers). Where...

Hi Anton, I ran llc with -verify-coalescing. There were no error messages. Then I added code in MipsPassConfig::addPreEmitPass() to prevent machine verifier from running post delay -slot-filler, and ran llc again. Again, there were no error messages. This is the list of passes run after post-RA scheduling. machine verifier is run twice after post RA scheduler (and CriticalAntiDepBreaker) is run. Post RA top-down li...

Dear developers. My question is the same as the title. Is there any way to implement target specific optimizations after instruction selection or later? I cannot find any related document. Please let me know. Thanks in advance. Minwook Ahn -------------- next part -------------- An HTML attachment was scrubbed... URL: