Displaying 4 results from an estimated 4 matches for "addpreemitpass2".
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addpreemitpass
2020 Nov 12
2
LLVM X86 MachineBasicBlock inserting push and pop instructions causes segmentation fault
...involves setting some global variables and calling a
function. I'm able to add the instructions and verify they get added, but
when the compiled program runs, it stops with a segfault.
For brevity, I'm not sharing the whole code here but basically I have a X86
MachineFunctionPass added to addPreEmitPass2 stage which simply inserts a
push rcx immediately followed by pop rcx before each basic block (only the
relevant logic portions are included):
/* Inserts push rcx followed by pop rcx before each MachineBasicBlock */
void VirtualTimeManager::__insertVtlLogic(MachineFunction &MF,
MachineBasi...
2018 Jun 30
2
Using BuildMI to insert Intel MPX instruction BNDCU failed
Hello everyone, I'm a newbie of llvm. I'm trying to insert Intel MPX
instruction BNDCU with BuildMI. I add my machinefunctionpass
at addPreEmitPass2.
Here is the code of insertion:
BuildMI(MBB, MI, DL, TII->get(X86::BNDCU64rr)).addReg(X86::BND2,
RegState::Define).addReg(X86::R10);
And here is to stack track when I compiler program with modified llc:
/home/shenyouren/workspace/build-llvm/bin/llc -o obj/simple.s
obj/simple-opt.bc
llc: /home...
2020 Nov 12
0
LLVM X86 MachineBasicBlock inserting push and pop instructions causes segmentation fault
...lobal variables and calling a
> function. I'm able to add the instructions and verify they get added, but
> when the compiled program runs, it stops with a segfault.
>
> For brevity, I'm not sharing the whole code here but basically I have a
> X86 MachineFunctionPass added to addPreEmitPass2 stage which simply inserts
> a push rcx immediately followed by pop rcx before each basic block (only
> the relevant logic portions are included):
>
> /* Inserts push rcx followed by pop rcx before each MachineBasicBlock */
> void VirtualTimeManager::__insertVtlLogic(MachineFunction...
2018 Jun 13
12
RFC: Atomic LL/SC loops in LLVM revisited
...to SelectionDAG right now.
Supporting only strong cmpxchg and using the success ordering for the failure
case is conservative but correct I believe.
In the RISC-V case, the LL/SC loop pseudo-instructions are lowered at the
latest possible moment. The RISCVExpandPseudoInsts pass is registered with
addPreEmitPass2.
The main aspect I'm unhappy with in this approach is the need to introduce new
intrinsics. Ideally these would be documented as not for use by frontends and
subject to future removal or alteration - is there precedent for this?
Alternatively, see the suggestion below to introduce target-indep...