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addpd
2009 Jun 17
0
[LLVMdev] help with tablegen
...h as well as
TableGen/IntrinsicEmitter.cpp and TableGen/CodeGenTarget.cpp where they
have switch(mvt). The actual patch is attached.
This runs into trouble with the X86 backend where the SSE2 forms of ADD
are defined:
llvm[3]: Building X86.td DAG instruction selector implementation with tblgen
ADDPDrm: (set:isVoid VR128:isFP:$dst, (fadd:isFP
VR128:isFP:$src1, (ld:isFP
addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
/home/nicholas/llvm-commit/Debug/bin/tblgen: error:
Included from X86.td:128:
Included from X86In...