Displaying 6 results from an estimated 6 matches for "addpd".
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2013 Jul 19
0
[LLVMdev] llvm.x86.sse2.sqrt.pd not using sqrtpd, calling a function that modifies ECX
...lpd xmm6,xmm4
002E01A8 mulpd xmm3,xmm7
002E01AC movapd xmm7,xmmword ptr [esp+60h]
002E01B2 subpd xmm7,xmm2
002E01B6 subpd xmm7,xmm3
002E01BA subpd xmm7,xmm5
002E01BE movapd xmm2,xmmword ptr [esi+2C0020h]
002E01C6 mulpd xmm2,xmm7
002E01CA addpd xmm2,xmm6
002E01CE movapd xmm5,xmmword ptr [esp+80h]
002E01D7 subpd xmm5,xmm1
002E01DB subpd xmm5,xmm3
002E01DF mulpd xmm0,xmmword ptr ds:[2E0010h]
002E01E7 subpd xmm5,xmm0
002E01EB movapd xmm6,xmmword ptr [esi+2C0040h]
002E01F3 mulpd xmm6...
2013 Jul 19
4
[LLVMdev] SIMD instructions and memory alignment on X86
Hmm, I'm not able to get those .ll files to compile if I disable SSE and I
end up with SSE instructions(including sqrtpd) if I don't disable it.
On Thu, Jul 18, 2013 at 10:53 PM, Peter Newman <peter at uformia.com> wrote:
> Is there something specifically required to enable SSE? If it's not
> detected as available (based from the target triple?) then I don't think
2013 Jul 20
1
[LLVMdev] Another memory alignment issue with SSE operations
Unfortunately, I've ran into a second issue where addpd is being
performed on memory that isn't 16 byte aligned. Again, this only happens
if the createJIT OptLevel is set to Default (vs None).
According to
http://www.jaist.ac.jp/iscenter-new/mpc/altix/altixdata/opt/intel/vtune/doc/users_guide/mergedProjects/analyzer_ec/mergedProjects/reference_ol...
2020 Aug 20
2
Question about llvm vectors
Hi Craig,
Thank you very much for your answer.
I did not want to discuss exactly the semantic and name of one operation
but instead raise the question "would it be beneficial to have more vector
builtins?".
You wrote that the compiler will recognize a pattern and replace it by
__builtin_ia32_haddps when possible, but how can I be sure of that? I would
have to disassemble the generated
2010 Apr 27
0
[LLVMdev] Proposal for a new LLVM concurrency memory model
On Monday 26 April 2010 16:09:48 Jeffrey Yasskin wrote:
> > Vector atomics are extremely useful on architectures that support them.
>
> I'm curious about the architectures/instructions you're thinking of.
> Something like 'lock; movdqa'?
Don't think X86. Think traditional vector machines like the Cray X1/X2.
Atomic vector adds and logicals are common
2010 Apr 26
2
[LLVMdev] Proposal for a new LLVM concurrency memory model
On Mon, Apr 26, 2010 at 1:09 PM, David Greene <dag at cray.com> wrote:
> On Monday 26 April 2010 14:03:35 Chandler Carruth wrote:
>> We can allow the IR to represent vectors, but unless hardware supports it,
>> I think lowering these by decomposing them is more than LLVM should try to
>> do. Because of that, I'm not sure we should support vectors as elsewhere