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addi
2009 Dec 08
2
[LLVMdev] Back-end with general purpose registers
Hi all,
I am trying to write a back-end for LLVM where any instruction may take
any type of data. I am looking for the output to be of the format:
inst.type reg1,reg2
etc. Where inst is the instruction, e.g. mov and type is data-type e.g.
f32 etc. I tried creating a back-end with a register class which could
take i32 and f32:
def GPRegs
: RegisterClass <"Test",