Displaying 6 results from an estimated 6 matches for "addmemoperands".
2013 Jan 18
0
[LLVMdev] llvm backend porting question ,
I start my porting for picoblaze,the soft cpu for fpga ,which is
designed by XILINX from MSP430 porting .
After some day's work , somethinig looks good , for it can generate
for some simple C program:
eg :
int f1(int a)
{
return a+1;
}
but it failed with this :
char f()
{
char a;
a++; a++; a++; a++; a++; a++; a++; a++; a++; a++; a++;
a++; a++; a++; a++;
2008 Jul 16
1
[LLVMdev] atomic memoperand patch
Just noticed that when we generate a custom lowering for some atomics
that we forgot to transfer the MemOperand to the new instruction that
touches memory.
-- Mon Ping
Index: lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- lib/Target/X86/X86ISelLowering.cpp (revision 53702)
+++ lib/Target/X86/X86ISelLowering.cpp (working copy)
@@
2011 Jan 25
1
[LLVMdev] Trouble with virtual registers
I'm having trouble with virtual registers/register allocation in my
back-end. Basically the FastRegAlloc pass is generating calls to
storeToStackSlot and loadFromStackSlot, in which we build new machine
instructions, which are then _not_ processed by the reg allocator. I
understand that BuildMI is changing the list of MachInst. that the allocator
is iterating over, but we need to have a new
2018 Sep 28
3
error: expected memory with 32-bit signed offset
Hi,
I want to encode Loongson ISA initially
https://gist.github.com/xiangzhai/8ae6966e2f02a94e180dd16ff1cd60ac
gslbx $2,0($3,$4)
It is equivalent to:
dadd $1, $3, $4
lb $2,0($1)
I just use mem_simmptr as the default value of DAGOperand MO ,
because MipsMemAsmOperand use parseMemOperand to parse general
MemOffset and only *one* AnyRegister , for example:
0($1)
But
2012 Mar 30
1
[LLVMdev] load instruction memory operands value null
Hi,
For a custom target, there is a pass to perform memory dependence analysis, where, i need to get memory pointer for "load instruction". I want to check the pointer alias behavior. I am getting this by considering the memoperands for the load instruction.
For "load instruction", Machine Instruction dumps as below:
vr12<def> = LD_Iri %vr2<kill>, 0;
2020 Jan 21
2
MASM & RIP-relative addressing
Are you asking what the parsing rules are, or how you should modify the LLVM code to achieve that result?
If the latter, you haven’t really given enough detail here. What code, exactly, have you tried modifying? Do you have any ideas for how it could work?
-Eli
From: Eric Astor <epastor at google.com>
Sent: Tuesday, January 21, 2020 2:44 PM
To: Eli Friedman <efriedma at